CLAIMS

1. A device (10) for testing a bit sequence generated by a Random Number Generator (1 1 ), wherein the device is configured to apply one or more statistical tests (103) to the bit sequence, in response the detection of N bits generated by the

Random number generator (1 1 ), each statistical test providing at least one sum value derived from the bits of said sequence, the testing device comprising:

- a comparator for comparing at least one test parameter related to each statistical test to one or more thresholds;

- a validation unit (105) configured to determine if said bit sequence is valid depending on the comparison made by the comparator for each statistical test;

wherein at least one of said test parameter and said at least one threshold is determined from N and from a target error probability.

2. The device of claim 1 , wherein said at least one or more statistical tests (103) applied to the sequence comprise a set of statistical tests providing at least one sum value derived from the bits of said sequence, which provides said at least one test parameter for each statistical test, the device further comprising:

- a threshold determination unit (101 ) for determining, for each statistical test of said set of statistical test, a lower threshold and a higher threshold from N and from the target error probability in association with each sum value;

wherein the comparator (102) is configured to compare, for each statistical test, each sum value to the associated lower threshold and higher threshold.

3. The device of claim 2, wherein the comparator is configured to output a validation bit for a statistical test, if each sum value is strictly superior to the associated lower threshold and strictly inferior to the higher threshold.

4. The device of claim 3, wherein the validation unit is configured to reject the bit sequence if at least one sum value for a statistical test is inferior or equal to the associated lower threshold or superior or equal to the corresponding higher threshold.

5. The device of any preceding claim 2 to 4, wherein the statistical tests (103) comprise the AIS Monobit Test which provides a sum value T_{1} the corresponding lower threshold L_{x} and the higher threshold H_{x} being equal to:

with a representing the target error probability.

6. The device of any preceding claim 2 to 5, wherein the statistical tests (103) comprise the AIS Poker Test which provide a sum value T_{2}, the corresponding lower threshold L_{2} and the higher threshold H_{2} being equal to:

with M representing the length of the contiguous blocks in the bit sequence and a representing the error probability.

7. The device of any preceding claim 2 to 6, wherein the statistical tests (103) comprise the AIS runs Test which provides a sum value T_{3(N k)} for each run of length k, the lower threshold L_{3 k} and the higher threshold H_{3 k} for each run of length k being equal to:

with a representing the target error probability and

8. The device of any preceding claim, wherein said at least one or more statistical tests (103) applied to the sequence comprise an additional set of statistical tests, the testing device determining, for each statistical test, a test parameter determined from N and from the error probability.

9. The device of claim 8, wherein the statistical tests (103) comprises the AIS Longest Run Test, the test parameter being a run length k , said length k being determined according to the following equation:

where a designates the long run probability,

wherein the comparator comparing said test parameter k to the run of maximal length.

10. The device of any preceding claim, wherein the bit sequence length N is changed between one or more clock cycles.

11. The device of any preceding claim 1 to 10, wherein a new value for the error probability and the number N may be received at different times or simultaneously.

12. A system implemented on at least one integrated circuits, said system comprising a device using a random bit sequence generated by a random number generator (1 1 ), wherein said device further comprises a testing device according to any of the preceding claim 1 to 1 1 for testing each random bit sequence generated by said random number generator.

13. A method for testing a bit sequence generated by a Random Number Generator (1 1 ), wherein the method comprises applying one or more statistical tests (103) to the bit sequence, in response the detection of N bits generated by the Random number generator (1 1 ), each statistical test providing at least one test parameter from the bits of said sequence, the testing method comprising:

- comparing at least one test parameter related to each statistical test to one or more thresholds;

- determining if said bit sequence is valid depending on the comparison performed for each statistical test in said comparing step;

wherein at least one of said test parameter and said at least one threshold is determined from N and from a target error probability.