Processing

Please wait...

Settings

Settings

Goto Application

1. WO2018125162 - SEMICONDUCTOR PACKAGE HAVING PASSIVE SUPPORT WAFER

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

CLAIMS

What is claimed is:

1. A semiconductor package, comprising:

an active die wafer having a top surface;

a plurality of active dies mounted on the top surface of the active die wafer; and a passive support wafer mounted on the plurality of active dies over the top surface of the active die wafer, wherein the passive support wafer includes a non-polymeric material.

2. The semiconductor package of claim 1, wherein the passive support wafer is a monolith of the non-polymeric material.

3. The semiconductor package of claim 2, wherein the passive support wafer has a passive support wafer thickness of less than 1 mm.

4. The semiconductor package of claim 3, wherein the non-polymeric material is one or more of a metal, a ceramic, a silicon, or a synthetic diamond.

5. The semiconductor package of claim 1, wherein the passive support wafer includes a bottom surface facing the top surface of the active die wafer, and wherein the top surface and the bottom surface have a same profile.

6. The semiconductor package of claim 1 further comprising a bonding layer between the plurality of active dies and the passive support wafer.

7. The semiconductor package of claim 6, wherein the bonding layer has a bonding layer thickness of 10-20 microns.

8. The semiconductor package of claim 7, wherein the bonding layer includes one or more of a die attach adhesive or a solder.

9. The semiconductor package of claim 6 further comprising an epoxy layer surrounding the plurality of active dies between the bonding layer and the active die wafer, wherein the bonding layer physically separates the passive support wafer from the epoxy layer and the plurality of active dies, and wherein the bonding layer thermally couples the passive support wafer to the plurality of active dies.

10. A semiconductor package assembly, comprising:

a printed circuit board; and

a semiconductor package mounted on the printed circuit board, the semiconductor package including:

an active die wafer having a top surface,

a plurality of active dies mounted on the top surface of the active die wafer, and

a passive support wafer mounted on the plurality of active dies over the top surface of the active die wafer, wherein the passive support wafer includes a non-polymeric material.

11. The semiconductor package assembly of claim 10 further comprising:

a heat spreader over the passive support wafer; and

a thermal interface layer between the heat spreader and the passive support wafer, wherein the thermal interface layer thermally couples the heat spreader to the passive support wafer.

12. The semiconductor package assembly of claim 10, wherein the passive support wafer is a monolith of the non-polymeric material.

13. The semiconductor package assembly of claim 12, wherein the passive support wafer has a passive support wafer thickness of less than 1 mm.

14. The semiconductor package assembly of claim 10 further comprising a bonding layer between the plurality of active dies and the passive support wafer.

15. The semiconductor package assembly of claim 14, wherein the bonding layer has a bonding layer thickness of 10-20 microns.

16. A method, comprising:

mounting a plurality of active dies on an active die wafer; and

mounting a passive support wafer on the plurality of active dies, wherein the passive support wafer includes a non-polymeric material.

17. The method of claim 16 further comprising:

processing a through-silicon-via in the active die wafer after mounting the passive support wafer on the plurality of active dies.

18. The method of claim 16, wherein mounting the passive support wafer on the plurality of active dies includes:

applying a bonding layer over the plurality of active dies, and

placing the passive support wafer on the bonding layer.

19. The method of claim 18, wherein the passive support wafer has a passive support wafer thickness of less than 1 mm, and wherein the bonding layer has a bonding layer thickness of 10-20 mm.

20. The method of claim 19 further comprising:

thinning the passive support wafer to the passive support wafer thickness.