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1. WO2021041159 - POWER OPTIMIZATION FOR MEMORY SUBSYSTEMS

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[ EN ]

CLAIMS

What is claimed is:

1. A method comprising:

initializing a drive strength value of a memory subsystem to a first level;

executing an operation on the memory subsystem with the drive strength at the first level;

determining that a bit error rate occurring in the memory subsystem as a result of executing the operation satisfies a threshold value; and

in response to determining that the bit error rate satisfies the threshold value, increasing the drive strength value of the memory subsystem to a second level.

2. The method of claim 1, further comprising:

re-executing the operation at the increased drive strength value of the memory subsystem;

determining, based on re-executing the operation at the increased drive strength value, that the bit error rate is within the threshold value;

maintaining the drive strength value of the memory subsystem at the second level; and returning results of re-executing the operation at the increased drive strength value to a host system.

3. The method of claim 2, further comprising:

determining an updated bit error rate based on re-executing the operation at the increased drive strength;

determining that the updated bit error rate satisfies the threshold value;

applying an error correcting code (ECC) to correct bit errors detected in data of the re- executed operation; and

returning the corrected data to a host system.

4. The method of claim 3, further comprising:

re-setting the drive strength value of the memory subsystem to a previous level.

5. The method of claim 1, further comprising:

detecting an occurrence of a power event in a host system; and

in response to detecting the power event, re-initializing the drive strength value of the memory subsystem to the first level.

6. The method of claim 5, wherein the power event comprises at least one of a sleep event, a power off event, or a reset event triggered by the host system.

7. The method of claim 5, wherein the power event is a timer-based event triggered by the host system or an event that is triggered when a threshold number of operations have been executed on the memory subsystem.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

initialize a drive strength value of a memory subsystem to a first level;

execute an operation on the memory subsystem with the drive strength at the first level; determine that a bit error rate occurring in the memory subsystem as a result of executing the operation on the memory subsystem satisfies a threshold value; in response to determining that the bit error rate satisfies the threshold value, increase the drive strength value of the memory subsystem to a second level;

re-execute the operation at the increased drive strength value of the memory subsystem; determine, based on re-executing the operation at the increased drive strength value, that the bit error rate does not satisfy the threshold value; and

maintain the drive strength value of the memory subsystem at the second level.

9. The non-transitory computer-readable medium of claim 8, wherein the processing device is further configured to return results of re-executing the operation at the increased drive strength value to a host system.

10. The non-transitory computer-readable medium of claim 8, wherein the processing device is further configured to:

determine an updated bit error rate based on re-executing the operation at the increased drive strength;

determine that the updated bit error rate satisfies the threshold value;

apply an error correcting code (ECC) to correct bit errors detected in data of the re- executed operation; and

return the corrected data to a host system.

11. The non-transitory computer-readable medium of claim 10, wherein the processing device is further configured to re-set the drive strength value of the memory subsystem to a previous level.

12. The non-transitory computer-readable medium of claim 10, wherein the processing device is further configured to:

detect an occurrence of a power event in the host system; and

in response to detecting the power event, re-initialize the drive strength value of the memory subsystem to the first level.

13. The non-transitory computer-readable medium of claim 12, wherein the power event comprises at least one of a sleep event, a power off event, or a reset event triggered by the host system.

14. The non-transitory computer-readable medium of claim 12, wherein the power event is a timer-based event triggered by the host system or an event that is triggered when a threshold number of operations have been executed on the memory subsystem.

15. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

initialize a drive strength value of a memory subsystem to a first level; execute an operation on the memory subsystem with the drive strength at the first level;

determine that a bit error rate occurring in the memory subsystem as a result of executing the operation satisfies a threshold value; and

in response to determining that the bit error rate satisfies the threshold value, increase the drive strength value of the memory subsystem to a second level.

16. The system of claim 15, wherein the processing device is further to:

re-execute the operation at the increased drive strength value of the memory subsystem; determine, based on re-executing the operation at the increased drive strength value, that the bit error rate is within the threshold value;

maintain the drive strength value of the memory subsystem at the second level; and return results of re-executing the operation at the increased drive strength value to a host system.

17. The system of claim 16, wherein the processing device is further to:

determine an updated bit error rate based on re-executing the operation at the increased drive strength;

determine that the updated bit error rate satisfies the threshold value;

apply an error correcting code (ECC) to correct bit errors detected in data of the re- executed operation; and

return the corrected data to a host system.

18. The system of claim 17, wherein the processing device is further configured to re-set the drive strength value of the memory subsystem to a previous level.

19. The system of claim 17, wherein the processing device is further configured to:

detect an occurrence of a power event in the host system; and

in response to detecting the power event, re-initialize the drive strength value of the memory subsystem to the first level.

20. The system of claim 19, wherein the power event comprises at least one of a sleep event, a power off event, or a reset event triggered by the host system.