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1. US20210066422 - ARRAY SUBSTRATE AND DISPLAY PANEL

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

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Claims

1. An array substrate having a base substrate, wherein the array substrate comprises:
a barrier layer disposed on and covering the base substrate;
a buffer layer disposed between the barrier layer and an active layer and covering the barrier layer;
the active layer disposed on the buffer layer;
a first gate insulating layer disposed on the active layer and covering the active layer and the buffer layer;
a first gate disposed on the first gate insulating layer;
a second gate insulating layer disposed on the first gate and covering the first gate and the first gate insulating layer;
a second gate disposed on the second gate insulating layer;
a first interlayer dielectric layer disposed on the second gate and covering the second gate and the second gate insulating layer;
a second interlayer dielectric layer disposed on and covering the first interlayer dielectric layer, and made of an organic material;
a source and a drain disposed on the second interlayer dielectric layer and connected to the active layer through a first via hole;
a passivation layer disposed on the source and drain and covering the source and drain and the second interlayer dielectric layer, and made of an inorganic material; and
a planarization layer disposed on and covering the passivation layer,
wherein the array substrate comprises a display area and a non-display area surrounding the display area, at least one first deep hole is provided in the display area, the first deep hole penetrates the first interlayer dielectric layer and extends to the barrier layer, and the first deep hole is filled with the second interlayer dielectric layer; and
wherein at least one second deep hole is provided in the non-display area, the second deep hole penetrates the first interlayer dielectric layer and extends to the base substrate, and the second deep hole is filled with the second interlayer dielectric layer.
2. The array substrate according to claim 1, wherein the array substrate further comprises an auxiliary electrode, which is disposed on the planarization layer, and is electrically connected to the drain through a second via hole.
3. The array substrate according to claim 2, wherein the array substrate further comprises at least one first electrode, which is disposed on the planarization layer and is electrically connected to the auxiliary electrode.
4. The array substrate according to claim 3, wherein the array substrate further comprises a pixel definition layer, which is disposed on the first electrode and covers the first electrode and the planarization layer, and the pixel definition layer has at least one opening, and each of the at least one opening exposes the first electrode.
5. The array substrate according to claim 4, wherein the array substrate further comprises at least one spacer, which is disposed on the pixel definition layer.
6. An array substrate having a base substrate, wherein the array substrate comprises:
an active layer disposed on the base substrate;
a first gate insulating layer disposed on the active layer and covering the active layer and the base substrate;
a first gate disposed on the first gate insulating layer;
a first interlayer dielectric layer disposed on the first gate and covering the first gate and the first gate insulating layer;
a second interlayer dielectric layer disposed on and covering the first interlayer dielectric layer, and made of an organic material;
a source and a drain disposed on the second interlayer dielectric layer and connected to the active layer through a first via hole;
a passivation layer disposed on the source and drain and covering the source and drain and the second interlayer dielectric layer, and made of an inorganic material; and
a planarization layer disposed on and covering the passivation layer.
7. The array substrate according to claim 6, wherein the array substrate further comprises a barrier layer disposed on and covering the base substrate.
8. The array substrate according to claim 7, wherein the array substrate further comprises a buffer layer disposed between the barrier layer and the active layer and covering the barrier layer.
9. The array substrate according to claim 7, wherein the array substrate further comprises:
a second gate insulating layer disposed on the first gate and covering the first gate and the first gate insulating layer; and
a second gate disposed on the second gate insulating layer.
10. The array substrate according to claim 7, wherein the array substrate comprises a display area and a non-display area surrounding the display area, at least one first deep hole is provided in the display area, the first deep hole penetrates the first interlayer dielectric layer and extends to the barrier layer, and the first deep hole is filled with the second interlayer dielectric layer; and
wherein at least one second deep hole is provided in the non-display area, the second deep hole penetrates the first interlayer dielectric layer and extends to the base substrate, and the second deep hole is filled with the second interlayer dielectric layer.
11. The array substrate according to claim 6, wherein the array substrate further comprises an auxiliary electrode, which is disposed on the planarization layer, and is electrically connected to the drain through a second via hole.
12. The array substrate according to claim 11, wherein the array substrate further comprises at least one first electrode, which is disposed on the planarization layer and is electrically connected to the auxiliary electrode.
13. The array substrate according to claim 12, wherein the array substrate further comprises a pixel definition layer, which is disposed on the first electrode and covers the first electrode and the planarization layer, and the pixel definition layer has at least one opening, and each of the at least one opening exposes the first electrode.
14. The array substrate according to claim 13, wherein the array substrate further comprises at least one spacer, which is disposed on the pixel definition layer.
15. A display panel comprising an array substrate, wherein the array substrate comprises:
an array substrate having a base substrate, wherein the array substrate comprises:
an active layer disposed on the base substrate;
a first gate insulating layer disposed on the active layer and covering the active layer and the base substrate;
a first gate disposed on the first gate insulating layer;
a first interlayer dielectric layer disposed on the first gate and covering the first gate and the first gate insulating layer;
a second interlayer dielectric layer disposed on and covering the first interlayer dielectric layer, and made of an organic material;
a source and a drain disposed on the second interlayer dielectric layer and connected to the active layer through a first via hole;
a passivation layer disposed on the source and drain and covering the source and drain and the second interlayer dielectric layer, and made of an inorganic material; and
a planarization layer disposed on and covering the passivation layer.