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1. WO2020140202 - METHOD FOR FORMING DUAL DAMASCENE INTERCONNECT STRUCTURE

Publication Number WO/2020/140202
Publication Date 09.07.2020
International Application No. PCT/CN2019/070118
International Filing Date 02.01.2019
IPC
H01L 21/768 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 21/311 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105After-treatment
311Etching the insulating layers
CPC
H01L 21/31144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31144using masks
H01L 21/76808
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76807for dual damascene structures
76808involving intermediate temporary filling with material
H01L 21/76811
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76807for dual damascene structures
76811involving multiple stacked pre-patterned masks
H01L 21/76813
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76807for dual damascene structures
76813involving a partial via etch
H01L 21/76829
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76829characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • XU, Jian
  • XIAO, Liang
  • DONG, Jin Wen
  • YAN, Meng
  • XIAO, Li Hong
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR FORMING DUAL DAMASCENE INTERCONNECT STRUCTURE
(FR) PROCÉDÉ DE FORMATION D'UNE STRUCTURE D'INTERCONNEXION À DOUBLE DAMASQUINAGE
Abstract
(EN)
A method for forming a dual damascene interconnect structure. A substrate having a conductor layer, an etch stop layer on the conductor layer, a dielectric stack on the etch stop layer, and a hard mask layer on the dielectric stack is provided. A photoresist layer having a resist opening is formed on the hard mask layer. The hard mask layer is etched through the resist opening to form a hard mask opening. The dielectric stack is etched through the hard mask opening to form a partial via hole. The photoresist layer is trimmed to form a widened resist opening above the partial via hole. The hard mask layer is etched through the widened resist opening to form a widened hard mask opening above the partial via hole. The dielectric stack is etched through the widened hard mask opening and the partial via hole to form a dual damascene via.
(FR)
L'invention concerne un procédé de formation d'une structure d'interconnexion à double damasquinage. Un substrat ayant une couche conductrice, une couche d'arrêt de gravure sur la couche conductrice, un empilement diélectrique sur la couche d'arrêt de gravure, et une couche de masque dur sur l'empilement diélectrique sont fournis. Une couche de résine photosensible ayant une ouverture de réserve est formée sur la couche de masque dur. La couche de masque dur est gravée à travers l'ouverture de réserve pour former une ouverture de masque dur. L'empilement diélectrique est gravé à travers l'ouverture de masque dur pour former un trou d'interconnexion partiel. La couche de résine photosensible est rognée pour former une ouverture de réserve élargie au-dessus du trou d'interconnexion partiel. La couche de masque dur est gravée à travers l'ouverture de réserve élargie pour former une ouverture de masque dur élargie au-dessus du trou d'interconnexion partiel. L'empilement diélectrique est gravé à travers l'ouverture de masque dur élargie et le trou d'interconnexion partiel pour former un trou d'interconnexion à double damasquinage.
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