(12) International Application Status Report

Received at International Bureau: 16 May 2019 (16.05.2019)

Information valid as of: 15 October 2020 (15.10.2020)

Report generated on: 07 March 2021 (07.03.2021)

(10) Publication number: (43) Publication date: (26) Publication language:
WO 2020/22027405 November 2020 (05.11.2020) English (EN)

(21) Application number: (22) Filing date: (25) Filing language:
PCT/CN2019/08521930 April 2019 (30.04.2019) English (EN)


(51) International Patent Classification:
G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 5/14 (2006.01)

(71) Applicant(s):
YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN/CN]; Room 7018, No.18, Huaguang Road Guandong Science and Technology Industrial Park East Lake Development Zone Wuhan, Hubei 430074 (CN) (for all designated states)

(72) Inventor(s):
CHEN, Weirong; Room 7018, No.18, Huaguang Road Guandong Science and Technology Industrial Park East Lake Development Zone Wuhan, Hubei 430074 (CN)
TANG, Qiang; Room 7018, No.18, Huaguang Road Guandong Science and Technology Industrial Park East Lake Development Zone Wuhan, Hubei 430074 (CN)

(74) Agent(s):
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.; 10th Floor, Tower C, Beijing Global Trade Center 36 North Third Ring Road East, Dongcheng District Beijing 100013 (CN)

(54) Title (EN): MEMORY SYSTEM CAPABLE OF REDUCING THE READING TIME
(54) Title (FR): SYSTÈME DE MÉMOIRE CAPABLE DE RÉDUIRE LE TEMPS DE LECTURE

(57) Abstract:
(EN): A bias circuit includes a charging current reproduce unit, a cell current reproduce unit, a current comparator, and a bit line bias generator. The charging current reproduce unit generates a charging reference voltage according to a charging current flowing through a voltage bias transistor. The cell current reproduce unit generates a cell reference voltage according to a cell current flowing through a common source transistor. The current comparator includes a first current generator for generating a replica charging current according to the charging reference voltage, and a second current generator for generating a replica cell current according to the cell reference voltage. The bit line bias generator generates a bit line bias voltage to control a page buffer for charging a bit line according to a difference between the replica charging current and the replica cell current.
(FR): L'invention concerne un circuit de polarisation qui comprend une unité de reproduction de courant de charge, une unité de reproduction de courant de cellule, un comparateur de courant, et un générateur de polarisation de ligne de bits. L'unité de reproduction de courant de charge génère une tension de référence de charge selon un courant de charge circulant à travers un transistor de polarisation de tension. L'unité de reproduction de courant de cellule génère une tension de référence de cellule selon un courant de cellule circulant à travers un transistor de source commune. Le comparateur de courant comprend un premier générateur de courant pour générer un courant de charge de réplique selon la tension de référence de charge, et un second générateur de courant pour générer un courant de cellule de réplique selon la tension de référence de cellule. Le générateur de polarisation de ligne de bits génère une tension de polarisation de ligne de bits afin de commander un tampon de page pour charger une ligne de bits selon une différence entre le courant de charge de réplique et le courant de cellule de réplique.

International search report:
Received at International Bureau: 06 February 2020 (06.02.2020) [CN]

International Report on Patentability (IPRP) Chapter II of the PCT:
Not available

(81) Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
European Patent Office (EPO) : AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR
African Intellectual Property Organization (OAPI) : BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG
African Regional Intellectual Property Organization (ARIPO) : BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW
Eurasian Patent Organization (EAPO) : AM, AZ, BY, KG, KZ, RU, TJ, TM