(12) International Application Status Report

Received at International Bureau: 18 December 2019 (18.12.2019)

Information valid as of: 15 May 2020 (15.05.2020)

Report generated on: 23 September 2020 (23.09.2020)

(10) Publication number: (43) Publication date: (26) Publication language:
WO 2020/11649911 June 2020 (11.06.2020) Japanese (JA)

(21) Application number: (22) Filing date: (25) Filing language:
PCT/JP2019/04738904 December 2019 (04.12.2019) Japanese (JA)

(31) Priority number(s): (32) Priority date(s): (33) Priority status:
2018-229754 (JP)07 December 2018 (07.12.2018) Priority document received (in compliance with PCT Rule 17.1)

(51) International Patent Classification:
H01L 29/786 (2006.01); H01L 21/336 (2006.01)

(71) Applicant(s):
NISSIN ELECTRIC CO., LTD. [JP/JP]; 47, Umezu Takase-cho, Ukyo-ku, Kyoto-shi, Kyoto 6158686 (JP) (for all designated states)

(72) Inventor(s):
MATSUO, Daisuke; c/o NISSIN ELECTRIC CO., LTD., 47, Umezu Takase-cho, Ukyo-ku, Kyoto-shi, Kyoto 6158686 (JP)
ANDO, Yasunori; c/o NISSIN ELECTRIC CO., LTD., 47, Umezu Takase-cho, Ukyo-ku, Kyoto-shi, Kyoto 6158686 (JP)


(54) Title (EN): THIN FILM TRANSISTOR AND PRODUCTION METHOD THEREFOR
(54) Title (FR): TRANSISTOR À COUCHES MINCES ET SON PROCÉDÉ DE PRODUCTION
(54) Title (JA): 薄膜トランジスタ及びその製造方法

(57) Abstract:
(EN): A thin film transistor having arranged, in order, upon a substrate: a gate electrode; a gate insulating layer; an oxide semiconductor layer; and a source electrode and a drain electrode. The thin film transistor is characterized by: the oxide semiconductor layer comprising, in order from the substrate side, a first semiconductor layer and a second semiconductor layer that comprise an oxide semiconductor film that has the same constituent element in both; and the crystallinity of the oxide semiconductor film constituting the second semiconductor layer being higher than the crystallinity of the oxide semiconductor film constituting the first semiconductor layer.
(FR): L'invention concerne un transistor à couches minces comportant, disposées dans l'ordre sur un substrat : une électrode grille ; une couche d'isolation de grille ; une couche semi-conductrice à oxyde ; et une électrode source et une électrode drain. Le transistor à couches minces est caractérisé en ce que : la couche semi-conductrice à oxyde comprend, dans l'ordre depuis le côté substrat, une première couche semi-conductrice et une seconde couche semi-conductrice qui comprennent un film semi-conducteur à oxyde ayant le même élément constitutif dans les deux couches ; et la cristallinité du film semi-conducteur à oxyde constituant la seconde couche semi-conductrice est supérieure à la cristallinité du film semi-conducteur à oxyde constituant la première couche semi-conductrice.
(JA): 基板上に、ゲート電極と、ゲート絶縁層と、酸化物半導体層と、ソース電極及びドレイン電極とがこの順に配置された薄膜トランジスタであって、前記酸化物半導体層は、互いに同一の構成元素を含む酸化物半導体膜から成る第1半導体層と第2半導体層とを前記基板側から順に備えており、前記第2半導体層を構成する酸化物半導体膜の結晶性が、前記第1半導体層を構成する前記酸化物半導体膜の結晶性よりも高いことを特徴とする薄膜トランジスタ。

International search report:
Received at International Bureau: 24 February 2020 (24.02.2020) [JP]

International Report on Patentability (IPRP) Chapter II of the PCT:
Not available

(81) Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
European Patent Office (EPO) : AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR
African Intellectual Property Organization (OAPI) : BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG
African Regional Intellectual Property Organization (ARIPO) : BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW
Eurasian Patent Organization (EAPO) : AM, AZ, BY, KG, KZ, RU, TJ, TM