(12) International Application Status Report

Received at International Bureau: 08 January 2019 (08.01.2019)

Information valid as of: 03 September 2020 (03.09.2020)

Report generated on: 30 September 2020 (30.09.2020)

(10) Publication number: (43) Publication date: (26) Publication language:
WO 2020/11369611 June 2020 (11.06.2020) Chinese (ZH)

(21) Application number: (22) Filing date: (25) Filing language:
PCT/CN2018/12291822 December 2018 (22.12.2018) Chinese (ZH)

(31) Priority number(s): (32) Priority date(s): (33) Priority status:
201811496462.1 (CN)07 December 2018 (07.12.2018) Priority document received (in compliance with PCT Rule 17.1)

(51) International Patent Classification:
H04R 19/04 (2006.01)

(71) Applicant(s):
WEIFANG GOERTEK MICROELECTRONICS CO., LTD. [CN/CN]; Building 10, Goer Phase II Industrial Park, No.102, Ronghua Road, Ronghua Community, Xincheng Sub-District Office, High-Tech Development Zone Weifang, Shandong 261031 (CN) (for all designated states)

(72) Inventor(s):
WANG, Dexin; No.268 Dongfang Road, Hi-Tech Industry District Weifang, Shandong 261031 (CN)
YANG, Junwei; No.268 Dongfang Road, Hi-Tech Industry District Weifang, Shandong 261031 (CN)
PAN, Xinchao; No.268 Dongfang Road, Hi-Tech Industry District Weifang, Shandong 261031 (CN)
DUANMU, Luyu; No.268 Dongfang Road, Hi-Tech Industry District Weifang, Shandong 261031 (CN)
QIU, Wenrui; No.268 Dongfang Road, Hi-Tech Industry District Weifang, Shandong 261031 (CN)


(54) Title (EN): COMBINED SENSOR
(54) Title (FR): CAPTEUR COMBINÉ
(54) Title (ZH): 组合传感器

(57) Abstract:
(EN): A combined sensor, the combined sensor comprising: a substrate (100), the substrate having an upper surface (110) and a lower surface; a first MEMS chip (310) and a first ASIC chip (320), the first MEMS chip (310) and the first ASIC chip (320) being mounted on the upper surface (110) of the substrate (100), the first MEMS chip (310) and the first ASIC chip (320) being electrically connected, and the first MEMS chip (310) having a capacitive structure; and a second MEMS chip (410) and a second ASIC chip (420), the second MEMS chip (410) and the second ASIC chip (420) bieng mounted on the upper surface (110) of the substrate (100), the second MEMS chip (410) and the second ASIC chip (420) being electrically connected, and the working voltage of the second MEMS chip (410) being an alternating current voltage. The shortest distance between the first MEMS chip (310) and the second ASIC chip (420) isd1, d1 ≥ 0.3mm; and the shortest distance between the first ASIC chip (320) and the second ASIC chip (420) being d2, d2 ≥ 1.2mm. Thus, a parasitic capacitance effect is reduced, thereby reducing electromagnetic induction, making the background noise of the first MEMS chip (310) greatly reduced when the combined sensor is operating, and improving the overall performance of the combined sensor.
(FR): La présente invention concerne un capteur combiné, le capteur combiné comprenant : un substrat (100), le substrat ayant une surface supérieure (110) et une surface inférieure ; une première puce MEMS (310) et une première puce ASIC (320), la première puce MEMS (310) et la première puce ASIC (320) étant montées sur la surface supérieure (110) du substrat (100), la première puce MEMS (310) et la première puce ASIC (320) étant connectées électriquement, et la première puce MEMS (310) ayant une structure capacitive ; et une seconde puce MEMS (410) et une seconde puce ASIC (420), la seconde puce MEMS (410) et la seconde puce ASIC (420) étant montées sur la surface supérieure (110) du substrat (100), la seconde puce MEMS (410) et la seconde puce ASIC (420) étant connectées électriquement, et la tension de travail de la seconde puce MEMS (410) étant une tension de courant alternatif. La distance la plus courte entre la première puce MEMS (310) et la seconde puce ASIC (420) est d1, d1 ≥ 0,3 mm ; et la distance la plus courte entre la première puce ASIC (320) et la seconde puce ASIC (420) étant d2, d2 ≥ 12 mm. Ainsi, un effet de capacité parasite est réduit, réduisant ainsi l'induction électromagnétique, rendant le bruit de fond de la première puce MEMS (310) fortement réduit lorsque le capteur combiné fonctionne, et améliorant la performance globale du capteur combiné.
(ZH): 一种组合传感器,组合传感器包括:基板(100),基板具有上表面(110)和下表面;第一MEMS芯片(310)和第一ASIC芯片(320),第一MEMS芯片(310)和第一ASIC芯片(320)安装至基板(100)的上表面(110),第一MEMS芯片(310)和第一ASIC芯片(320)电连接,第一MEMS芯片(310)为电容式结构;以及第二MEMS芯片(410)和第二ASIC芯片(420),第二MEMS芯片(410)和第二ASIC芯片(420)安装至基板(100)的上表面(110),第二MEMS芯片(410)和第二ASIC芯片(420)电连接,第二MEMS芯片(410)的工作电压为交流电压;第一MEMS芯片(310)和第二ASIC芯片(420)的最短距离为d1,d1≥0.3mm,第一ASIC芯片(320)和第二ASIC芯片(420)的最短距离为d2,d2≥1.2mm。能够减弱寄生电容效应,从而减小了电磁感应,使得组合传感器工作时,第一MEMS芯片(310)的本底噪声大幅度下降,提升了组合传感器的整体性能。

International search report:
Received at International Bureau: 30 August 2019 (30.08.2019) [CN]

International Report on Patentability (IPRP) Chapter II of the PCT:
Not available

(81) Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
European Patent Office (EPO) : AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR
African Intellectual Property Organization (OAPI) : BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG
African Regional Intellectual Property Organization (ARIPO) : BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW
Eurasian Patent Organization (EAPO) : AM, AZ, BY, KG, KZ, RU, TJ, TM