(12) International Application Status Report

Received at International Bureau: 09 October 2017 (09.10.2017)

Information valid as of: 04 July 2018 (04.07.2018)

Report generated on: 20 September 2019 (20.09.2019)

(10) Publication number: (43) Publication date: (26) Publication language:
WO 2019/06692604 April 2019 (04.04.2019) English (EN)

(21) Application number: (22) Filing date: (25) Filing language:
PCT/US2017/05441329 September 2017 (29.09.2017) English (EN)


(51) International Patent Classification:
H01L 29/786 (2006.01)

(71) Applicant(s):
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054 (US) (for all designated states)
SHARMA, Abhishek A. [IN/US]; 1091 NE Orenco Station Parkway E317 Hillsboro, Oregon 97124 (US) (for all designated states)
LE, Van H. [US/US]; 2453 NW Rogue Valley Terrace Beaverton, Oregon 97006 (US) (for all designated states)
DEWEY, Gilbert [US/US]; 920 SE 58th Avenue Hillsboro, Oregon 97123 (US) (for all designated states)
RACHMADY, Willy [ID/US]; 10945 SW Nutcracker Court Beaverton, Oregon 97007 (US) (for all designated states)

(72) Inventor(s):
SHARMA, Abhishek A.; 1091 NE Orenco Station Parkway E317 Hillsboro, Oregon 97124 (US)
LE, Van H.; 2453 NW Rogue Valley Terrace Beaverton, Oregon 97006 (US)
DEWEY, Gilbert; 920 SE 58th Avenue Hillsboro, Oregon 97123 (US)
RACHMADY, Willy; 10945 SW Nutcracker Court Beaverton, Oregon 97007 (US)

(74) Agent(s):
WANG, Yuke; SCHWABE, WILLIAMSON & WYATT, P.C. 1211 SW 5th, Ste 1900 Portland, Oregon 97204 (US)

(54) Title (EN): SPACER-PATTERNED INVERTERS BASED ON THIN-FILM TRANSISTORS
(54) Title (FR): ONDULEURS À MOTIFS D'ÉLÉMENTS D'ESPACEMENT BASÉS SUR DES TRANSISTORS EN COUCHES MINCES

(57) Abstract:
(EN): A semiconductor device may include a first gate electrode and a second gate electrode. A first channel area and a second channel area may be above the first gate electrode, where the first channel area may include a first type channel material, and the second channel area may include a second type channel material. A third channel area and a fourth channel area may be above the second gate electrode, where the third channel area may include the first type channel material, and the fourth channel area may include the second type channel material. The third channel area may be separated from the first channel area by a spacer. An inverter may include the first gate electrode, the first channel area, and the second channel area, while another inverter may include the second gate electrode, the third channel area, and the fourth channel area. Other embodiments may be described/claimed.
(FR): L'invention concerne un dispositif semi-conducteur pouvant comprendre une première électrode grille et une seconde électrode grille. Une première zone de canal et une seconde zone de canal peuvent être au-dessus de la première électrode grille, la première zone de canal pouvant comprendre un matériau de canal de premier type, et la seconde zone de canal pouvant comprendre un matériau de canal de second type. Une troisième zone de canal et une quatrième zone de canal peuvent être au-dessus de la deuxième électrode grille, la troisième zone de canal pouvant comprendre le matériau de canal de premier type, et la quatrième zone de canal pouvant comprendre le matériau de canal de second type. La troisième zone de canal peut être séparée de la première zone de canal par un élément d'espacement. Un onduleur peut comprendre la première électrode grille, la première zone de canal et la seconde zone de canal, tandis qu'un autre onduleur peut comprendre la deuxième électrode grille, la troisième zone de canal et la quatrième zone de canal. L'invention concerne également d'autres modes de réalisation.

International search report:
Received at International Bureau: 02 July 2018 (02.07.2018) [KR]

International Report on Patentability (IPRP) Chapter II of the PCT:
Not available

(81) Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
European Patent Office (EPO) : AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR
African Intellectual Property Organization (OAPI) : BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG
African Regional Intellectual Property Organization (ARIPO) : BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW
Eurasian Patent Organization (EAPO) : AM, AZ, BY, KG, KZ, RU, TJ, TM