(12) International Application Status Report

Received at International Bureau: 08 August 2018 (08.08.2018)

Information valid as of: 21 January 2019 (21.01.2019)

Report generated on: 24 July 2019 (24.07.2019)

(10) Publication number: (43) Publication date: (26) Publication language:
WO 2019/02480307 February 2019 (07.02.2019) Chinese (ZH)

(21) Application number: (22) Filing date: (25) Filing language:
PCT/CN2018/09753327 July 2018 (27.07.2018) Chinese (ZH)

(31) Priority number(s): (32) Priority date(s): (33) Priority status:
201710639905.7 (CN)31 July 2017 (31.07.2017) Priority document received (in compliance with PCT Rule 17.1)

(51) International Patent Classification:
H03K 19/0185 (2006.01)

(71) Applicant(s):
SANECHIPS TECHNOLOGY CO., LTD. [CN/CN]; ZTE Industrial Park, Liuxian Avenue Xili Street, Nanshan District Shenzhen, Guangdong 518055 (CN) (for all designated states)

(72) Inventor(s):
DANG, Tao; ZTE Plaza, Keji Road South, Hi-Tech Industrial Park, Nanshan District Shenzhen, Guangdong 518057 (CN)

(74) Agent(s):
TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS; Fan Zhang, 10th Floor, Tower D Minsheng Financial Center 28 Jianguomennei Avenue Dongcheng District, Beijing 100005 (CN)

(54) Title (EN): LEVEL SHIFTER CIRCUIT AND INTEGRATED CIRCUIT CHIP
(54) Title (FR): CIRCUIT DE DÉCALAGE DE NIVEAU ET PUCE DE CIRCUIT INTÉGRÉ
(54) Title (ZH): 电平移位电路和集成电路芯片

(57) Abstract:
(EN): Provided in the present disclosure are a level shifter circuit and an integrated circuit chip. In said level shifter circuit, access voltage division circuits are additionally arranged between the drain of a P-channel metal oxide semiconductor field effect transistor (PMOS) and the drain of an N-channel metal oxide semiconductor field effect transistor (NMOS), between the source and drain of the PMOS and between the source and drain of the NMOS respectively within a level shifter circuit composed of a first PMOS and a second PMOS that are cross-connected and a first NMOS and a second NMOS that serve as two low voltage domain inversion signal inputs.
(FR): La présente invention concerne un circuit de décalage de niveau et une puce de circuit intégré. Dans ledit circuit de décalage de niveau, des circuits de division de tension d'accès sont agencés de manière complémentaire entre le drain d'un transistor à effet de champ à semi-conducteur à oxyde métallique à canal P (PMOS) et le drain d'un transistor à effet de champ à semi-conducteur à oxyde métallique à canal N (NMOS), entre la source et le drain du PMOS et entre la source et le drain du NMOS respectivement dans un circuit de décalage de niveau composé d'un premier PMOS et d'un second PMOS qui sont connectés en croix et d'un premier NMOS et d'un second NMOS qui servent en tant que deux entrées de signal d'inversion de domaine basse tension.
(ZH): 本公开提供了一种电平移位电路和一种集成电路芯片。在所述电平移位电路中,在由交叉连接的第一P沟道场效应晶体管(PMOS)和第二PMOS以及作为两个低电压域反相信号输入的第一N沟道场效应晶体管(NMOS)和第二NMOS组成的电平移位电路中,在PMOS的漏极和NMOS的漏极之间、PMOS源极和漏极之间和NMOS源极和漏极之间分别增加设置接入分压电路。

International search report:
Received at International Bureau: 01 November 2018 (01.11.2018) [CN]

International Report on Patentability (IPRP) Chapter II of the PCT:
Not available

(81) Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
European Patent Office (EPO) : AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR
African Intellectual Property Organization (OAPI) : BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG
African Regional Intellectual Property Organization (ARIPO) : BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW
Eurasian Patent Organization (EAPO) : AM, AZ, BY, KG, KZ, RU, TJ, TM