(12) International Application Status Report

Received at International Bureau: 19 April 2017 (19.04.2017)

Information valid as of: 10 July 2017 (10.07.2017)

Report generated on: 26 January 2020 (26.01.2020)

(10) Publication number: (43) Publication date: (26) Publication language:
WO 2018/18979718 October 2018 (18.10.2018) Japanese (JA)

(21) Application number: (22) Filing date: (25) Filing language:
PCT/JP2017/01472510 April 2017 (10.04.2017) Japanese (JA)


(51) International Patent Classification:
H05K 3/20 (2006.01)

(71) Applicant(s):
HITACHI CHEMICAL COMPANY, LTD. [JP/JP]; 9-2, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1006606 (JP) (for all designated states)

(72) Inventor(s):
NISHIYAMA, Tomoo; c/o Hitachi Chemical Company, Ltd., 9-2, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1006606 (JP)
TOGAWA, Mitsuo; c/o Hitachi Chemical Company, Ltd., 9-2, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1006606 (JP)
TAKEZAWA, Yoshitaka; c/o Hitachi Chemical Company, Ltd., 9-2, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1006606 (JP)
NAKAMURA, Yuki; c/o Hitachi Chemical Company, Ltd., 9-2, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1006606 (JP)
KIGUCHI, Kazuya; c/o Hitachi Chemical Company, Ltd., 9-2, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1006606 (JP)
MIYAZAKI, Yasuo; c/o Hitachi Chemical Company, Ltd., 9-2, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1006606 (JP)
AMANUMA, Shinji; c/o Hitachi Chemical Company, Ltd., 9-2, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1006606 (JP)

(74) Agent(s):
TAIYO, NAKAJIMA & KATO; 3-17, Shinjuku 4-chome, Shinjuku-ku, Tokyo 1600022 (JP)

(54) Title (EN): CIRCUIT BOARD PRODUCTION METHOD, CIRCUIT SHEET AND CIRCUIT BOARD
(54) Title (FR): PROCÉDÉ DE PRODUCTION DE CARTE DE CIRCUITS, FEUILLE DE CIRCUITS ET CARTE DE CIRCUITS
(54) Title (JA): 回路基板の製造方法、回路シート及び回路基板

(57) Abstract:
(EN): This circuit board production method comprises the step of disposing, over a board, a circuit sheet comprising circuits and a resin portion provided in the space between the circuits.
(FR): La présente invention concerne un procédé de production de carte de circuits qui comprend l'étape consistant à disposer, sur une carte, une feuille de circuits comprenant des circuits et une partie en résine disposée dans l'espace entre les circuits.
(JA): 回路と、前記回路の間の空間に設けられる樹脂部と、を備える回路シートを基板上に配置する工程を備える、回路基板の製造方法。

International search report:
Received at International Bureau: 10 July 2017 (10.07.2017) [JP]

International Report on Patentability (IPRP) Chapter II of the PCT:
Not available

(81) Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
European Patent Office (EPO) : AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR
African Intellectual Property Organization (OAPI) : BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG
African Regional Intellectual Property Organization (ARIPO) : BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW
Eurasian Patent Organization (EAPO) : AM, AZ, BY, KG, KZ, RU, TJ, TM