(12) International Application Status Report

Received at International Bureau: 28 October 2017 (28.10.2017)

Information valid as of: 30 October 2017 (30.10.2017)

Report generated on: 25 March 2019 (25.03.2019)

(10) Publication number: (43) Publication date: (26) Publication language:
WO 2018/09351524 May 2018 (24.05.2018) English (EN)

(21) Application number: (22) Filing date: (25) Filing language:
PCT/US2017/05699817 October 2017 (17.10.2017) English (EN)

(31) Priority number(s): (32) Priority date(s): (33) Priority status:
15/354,291 (US)17 November 2016 (17.11.2016) Priority document received (in compliance with PCT Rule 17.1)

(51) International Patent Classification:
H01L 25/065 (2006.01); H01L 25/07 (2006.01); H01L 23/48 (2006.01)

(71) Applicant(s):
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054 (US) (for all designated states)

(72) Inventor(s):
CHEAH, Bok Eng; 15 Lorong Permai 4 Bukit Gambir, 11700 (MY)
LIM, Min Suet; 15, Lorong Cendana Permai 8 Taman Cendana Permai Simpang Ampat, 14100 (MY)
KONG, Jackson Chung Peng; 12A, Denai Bayu 12 Seri Tanjung Pinang Tanjung Tokong, 07, 10470 (MY)

(74) Agent(s):
PERDOK, Monique M.; Schwegman Lundberg & Woessner, P.A. P.O. Box 2938 Minneapolis, Minnesota 55402 (US)

(54) Title (EN): MICROELECTRONIC DEVICE PACKAGE HAVING ALTERNATELY STACKED DIE
(54) Title (FR): BOÎTIER DE DISPOSITIF MICROÉLECTRONIQUE AYANT UNE PUCE EMPILÉE EN ALTERNANCE

(57) Abstract:
(EN): A microelectronic device package including multiple layers of stacked die. Multiple die layers in the package can include two or more die. At least two die in a first layer will be laterally spaced from one another to define a first gap extending in a first direction; and at least two die in a second layer will be laterally spaced from one another to define a second gap extending in a second direction that is angularly offset from the first direction. The first and second directions can be perpendicular to one another.
(FR): L'invention concerne un boîtier de dispositif microélectronique comprenant de multiples couches de puces empilées. De multiples couches de puce dans le boîtier peuvent comprendre deux puces ou plus. Au moins deux puces dans une première couche seront espacées latéralement l'une de l'autre pour définir un premier espace s'étendant dans une première direction; et au moins deux puces dans une seconde couche seront latéralement espacées les unes des autres pour définir un second espace s'étendant dans une seconde direction qui est décalée angulairement par rapport à la première direction. Les première et seconde directions peuvent être perpendiculaires l'une à l'autre.

International search report:
Received at International Bureau: 01 February 2018 (01.02.2018) [KR]

International Report on Patentability (IPRP) Chapter II of the PCT:
Not available

(81) Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
European Patent Office (EPO) : AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR
African Intellectual Property Organization (OAPI) : BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG
African Regional Intellectual Property Organization (ARIPO) : BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW
Eurasian Patent Organization (EAPO) : AM, AZ, BY, KG, KZ, RU, TJ, TM