(12) International Application Status Report

Received at International Bureau: 10 August 2016 (10.08.2016)

Information valid as of: 26 September 2016 (26.09.2016)

Report generated on: 18 September 2019 (18.09.2019)

(10) Publication number: (43) Publication date: (26) Publication language:
WO 2018/02064001 February 2018 (01.02.2018) Japanese (JA)

(21) Application number: (22) Filing date: (25) Filing language:
PCT/JP2016/07215828 July 2016 (28.07.2016) Japanese (JA)


(51) International Patent Classification:
H01L 23/48 (2006.01); H01L 21/52 (2006.01)

(71) Applicant(s):
MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310 (JP) (for all designated states)

(72) Inventor(s):
NAKATA, Yosuke; c/o Mitsubishi Electric Corporation, 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310 (JP)
SASAKI, Taishi; c/o Mitsubishi Electric Corporation, 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310 (JP)

(74) Agent(s):
TAKADA, Mamoru; Takada, Takahashi & Partners, Konwa Bldg. 7F, 12-22 Tsukiji 1-chome, Chuo-ku, Tokyo 1040045 (JP)

(54) Title (EN): SEMICONDUCTOR DEVICE
(54) Title (FR): DISPOSITIF À SEMI-CONDUCTEURS
(54) Title (JA): 半導体装置

(57) Abstract:
(EN): A semiconductor chip (3) is bonded to an upper surface of an electrode substrate (1) via a first solder (2). A lead frame (5) is bonded to an upper surface of the semiconductor chip (3) via a second solder (4). Between the electrode substrate (1) and the semiconductor chip (3), an intermediate plate (6) is provided in the first solder (2). The yield strength of the intermediate plate (6) is higher than that of the electrode substrate (1) and that of the first solder (2) within the service temperature range of the semiconductor device.
(FR): Une puce semi-conductrice (3) est liée à une surface supérieure d'un substrat d'électrode (1) par l'intermédiaire d'une première soudure (2). Une grille de connexion (5) est liée à une surface supérieure de la puce semi-conductrice (3) par l'intermédiaire d'une seconde soudure (4). Entre le substrat d'électrode (1) et la puce semi-conductrice (3), une plaque intermédiaire (6) est prévue dans la première soudure (2). La limite d'élasticité de la plaque intermédiaire (6) est supérieure à celle du substrat d'électrode (1) et celle de la première soudure (2) dans la plage de température de service du dispositif à semi-conducteur.
(JA): 電極基板(1)の上面に第1のはんだ(2)を介して半導体チップ(3)が接合されている。半導体チップ(3)の上面に第2のはんだ(4)を介してリードフレーム(5)が接合されている。電極基板(1)と半導体チップ(3)との間において第1のはんだ(2)中に中間板(6)が設けられている。中間板(6)の耐力は、半導体装置の使用温度範囲の全てにおいて電極基板(1)及び第1のはんだ(2)の耐力よりも大きい。

International search report:
Received at International Bureau: 26 September 2016 (26.09.2016) [JP]

International Report on Patentability (IPRP) Chapter II of the PCT:
Not available

(81) Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
European Patent Office (EPO) : AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR
African Intellectual Property Organization (OAPI) : BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG
African Regional Intellectual Property Organization (ARIPO) : BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW
Eurasian Patent Organization (EAPO) : AM, AZ, BY, KG, KZ, RU, TJ, TM