| (12) International Application Status Report | ||
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| Received at International Bureau: 27 August 2014 (27.08.2014) | ||
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| Information valid as of: 04 February 2015 (04.02.2015) | ||
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| Report generated on: 27 February 2021 (27.02.2021) | ||
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| (10) Publication number: | (43) Publication date: | (26) Publication language: |
| WO 2015/025499 | 26 February 2015 (26.02.2015) | Japanese (JA) |
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| (21) Application number: | (22) Filing date: | (25) Filing language: |
| PCT/JP2014/004153 | 08 August 2014 (08.08.2014) | Japanese (JA) |
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| (31) Priority number(s): | (32) Priority date(s): | (33) Priority status: |
| 2013-169966 (JP) | 19 August 2013 (19.08.2013) | Priority document received (in compliance with PCT Rule 17.1) |
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| (51) International Patent Classification: | ||
| H01L 29/47 (2006.01); H01L 29/06 (2006.01); H01L 29/22 (2006.01); H01L 29/861 (2006.01); H01L 29/868 (2006.01); H01L 29/872 (2006.01) | ||
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| (71) Applicant(s): | ||
| IDEMITSU KOSAN CO.,LTD.
[JP/JP]; 1-1, Marunouchi 3-chome, Chiyoda-ku, Tokyo
1008321 (JP) (for all designated states)
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| (72) Inventor(s): | ||
| TOMAI, Shigekazu; 1280, Kamiizumi, Sodegaura-shi, Chiba
2990293
(JP)
SHIBATA, Masatoshi; 1280, Kamiizumi, Sodegaura-shi, Chiba 2990293 (JP) KAWASHIMA, Emi; 1280, Kamiizumi, Sodegaura-shi, Chiba 2990293 (JP) YANO, Koki; 1280, Kamiizumi, Sodegaura-shi, Chiba 2990293 (JP) HAYASAKA, Hiromi; 1280, Kamiizumi, Sodegaura-shi, Chiba 2990293 (JP) |
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| (74) Agent(s): | ||
| WATANABE, Kihei; Shibashin Kanda Bldg. 3rd Floor, 26, Kanda Suda-cho 1-chome, Chiyoda-ku, Tokyo
1010041 (JP)
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| (54) Title (EN): OXIDE SEMICONDUCTOR SUBSTRATE AND SCHOTTKY BARRIER DIODE | ||
| (54) Title (FR): SUBSTRAT SEMICONDUCTEUR À OXYDE ET DIODE À BARRIÈRE DE SCHOTTKY | ||
| (54) Title (JA): 酸化物半導体基板及びショットキーバリアダイオード | ||
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| (57) Abstract: | ||
| (EN): A Schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, wherein the oxide semiconductor layer contains a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0-5.6 eV, inclusive.
(FR): L'invention concerne un élément diode à barrière de Schottky comprenant un substrat en silicium (Si), une couche d'oxyde semiconductrice et une couche d'électrode de Schottky, la couche d'oxyde semiconductrice contenant un semiconducteur à oxyde polycristallin et/ou amorphe ayant une largeur de bande interdite de 3,0 à 5,6 eV y compris. (JA): シリコン(Ｓｉ)基板と、酸化物半導体層と、ショットキー電極層とを有するショットキーバリアダイオード素子であって、前記酸化物半導体層が、３.０ｅＶ以上、５.６ｅＶ以下のバンドギャップを有する多結晶及び／又は非晶質の酸化物半導体を含むショットキーバリアダイオード素子。 |
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| International search report: | ||
| Received at International Bureau: 17 November 2014 (17.11.2014) [JP] | ||
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| International Report on Patentability (IPRP) Chapter II of the PCT: | ||
| Not available | ||
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| (81) Designated States: | ||
| AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW | ||
| European Patent Office (EPO) : AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR | ||
| African Intellectual Property Organization (OAPI) : BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG | ||
| African Regional Intellectual Property Organization (ARIPO) : BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW | ||
| Eurasian Patent Organization (EAPO) : AM, AZ, BY, KG, KZ, RU, TJ, TM | ||
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