(12) International Application Status Report

Received at International Bureau: 25 October 2007 (25.10.2007)

Information valid as of: 03 April 2009 (03.04.2009)

Report generated on: 20 January 2021 (20.01.2021)

(10) Publication number: (43) Publication date: (26) Publication language:
WO 2009/04786516 April 2009 (16.04.2009) Japanese (JA)

(21) Application number: (22) Filing date: (25) Filing language:
PCT/JP2007/06998412 October 2007 (12.10.2007) Japanese (JA)


(51) International Patent Classification:
H04B 1/06 (2006.01); H04B 3/04 (2006.01)

(71) Applicant(s):
FUJITSU LIMITED [JP/JP]; 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi, Kanagawa 2118588 (JP) (for all designated states except US)
KIBUNE, Masaya [JP/JP]; c/o FUJITSU LIMITED, 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi, Kanagawa 2118588 (JP) (for US only)

(72) Inventor(s):
KIBUNE, Masaya; c/o FUJITSU LIMITED, 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi, Kanagawa 2118588 (JP)

(74) Agent(s):
AOKI, Atsushi; SEIWA PATENT & LAW Toranomon 37 Mori Bldg. 5-1, Toranomon 3-chome Minato-ku, Tokyo 1058423 (JP)

(54) Title (EN): RECEPTION CIRCUIT, CONVERSION TABLE GENERATING METHOD OF AD CONVERTER OF THE SAME AND SIGNAL TRANSMISSION SYSTEM
(54) Title (FR): CIRCUIT DE RÉCEPTION, PROCÉDÉ DE GÉNÉRATION DE TABLE DE CONVERSION D'UN CONVERTISSEUR AN DE CELUI-CI ET SYSTÈME DE TRANSMISSION DE SIGNAL
(54) Title (JA): 受信回路、受信回路のADコンバータの変換テーブル作成方法、および信号伝送システム

(57) Abstract:
(EN): A reception circuit (3) is provided with an AD converter (31) outputting digital data in accordance with an input signal, a correction circuit (50) correcting non-linearity of the AD converter and an equivalent circuit (32) equalizing corrected digital data, and the reception circuit corrects non-linearity of ADC. The correction circuit (50) is provided with a conversion table (55) converting digital data which the AD converter outputs and a correction amount operation part (54) generating a conversion table from output data of the AD converter and output of the equivalent circuit.
(FR): L'invention porte sur un circuit de réception (3) qui comporte un convertisseur AN (31) émettant des données numériques conformément à un signal d'entrée, un circuit de correction (50) corrigeant une non-linéarité du convertisseur AN et un circuit équivalent (32) égalisant des données numériques corrigées, et le circuit de réception corrige une non-linéarité de CAN. Le circuit de correction (50) comporte une table de conversion (55) convertissant des données numériques que le convertisseur AN émet et une partie de fonctionnement de quantité de correction (54) générant une table de conversion à partir de données de sortie du convertisseur AN et d'une sortie du circuit équivalent.
(JA):  入力信号に応じてデジタルデータを出力するADコンバータ31と、ADコンバータの非線形性を補正する補正回路50と、補正された前記デジタルデータを等化する等化回路32と、を備え、ADCの非線形性を補正するように構成された受信回路3で、補正回路50は、ADコンバータの出力するデジタルデータを変換する変換テーブル55と、ADコンバータの出力データと等化回路の出力から変換テーブルを作成する補正量演算部54と、を備える。

International search report:
Received at International Bureau: 17 January 2008 (17.01.2008) [JP]

International Report on Patentability (IPRP) Chapter II of the PCT:
Not available

(81) Designated States:
AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
European Patent Office (EPO) : AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR
African Intellectual Property Organization (OAPI) : BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG
African Regional Intellectual Property Organization (ARIPO) : BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW
Eurasian Patent Organization (EAPO) : AM, AZ, BY, KG, KZ, MD, RU, TJ, TM