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1. WO2022096226 - HALBLEITERMODUL MIT ZUMINDEST EINEM HALBLEITERELEMENT

Veröffentlichungsnummer WO/2022/096226
Veröffentlichungsdatum 12.05.2022
Internationales Aktenzeichen PCT/EP2021/077984
Internationales Anmeldedatum 11.10.2021
CPC
H01L 2224/04026
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04026Bonding areas specifically adapted for layer connectors
H01L 2224/04042
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
H01L 2224/0603
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
0601Structure
0603Bonding areas having different sizes, e.g. different heights or widths
H01L 2224/06181
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
061Disposition
0618being disposed on at least two different sides of the body, e.g. dual array
06181On opposite sides of the body
H01L 2224/08225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
07Structure, shape, material or disposition of the bonding areas after the connecting process
08of an individual bonding area
081Disposition
0812the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
08151the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
08221the body and the item being stacked
08225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/29007
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
29005Structure
29007Layer connector smaller than the underlying bonding area
Anmelder
  • SIEMENS AKTIENGESELLSCHAFT [DE]/[DE]
Erfinder
  • KNEISSL, Philipp
  • PFEFFERLEIN, Stefan
  • KÜRTEN, Bernd
  • WERNER, Ronny
Prioritätsdaten
20205478.903.11.2020EP
Veröffentlichungssprache Deutsch (de)
Anmeldesprache Deutsch (DE)
Designierte Staaten
Titel
(DE) HALBLEITERMODUL MIT ZUMINDEST EINEM HALBLEITERELEMENT
(EN) SEMICONDUCTOR MODULE HAVING AT LEAST ONE SEMICONDUCTOR ELEMENT
(FR) MODULE SEMI-CONDUCTEUR COMPRENANT AU MOINS UN ÉLÉMENT SEMI-CONDUCTEUR
Zusammenfassung
(DE) Die Erfindung betrifft ein Halbleitermodul (2) mit zumindest einem Halbleiterelement (4), wobei das Halbleiterelement (4) ein Kontaktierungselement (18) aufweist, wobei das Kontaktierungselement (18) des Halbleiterelements (4) über eine Verbindungsschicht (20) stoffschlüssig mit einer metallischen Oberfläche (14) verbunden ist. Um das Halbleitermodul (2), im Vergleich zum Stand der Technik, einfacher und zuverlässiger zu fertigen wird vorgeschlagen, dass die metallische Oberfläche (14) eine Kavität (22) aufweist in welcher die Verbindungsschicht (20) angeordnet ist, wobei das Kontaktierungselement (18) die Kavität (22) zumindest teilweise überlappt.
(EN) The invention relates to a semiconductor module (2) having at least one semiconductor element (4), wherein the semiconductor element (4) has a contacting element (18), and wherein the contacting element (18) of the semiconductor element (4) is integrally joined to a metal surface (14) by means of a joining layer (20). According to the invention, in order to produce the semiconductor module (2) more easily and more reliably in comparison with the prior art, the metal surface (14) has a cavity (22), in which the joining layer (20) is disposed, and the contacting element (18) at least partly overlaps the cavity (22).
(FR) L'invention concerne un module semi-conducteur (2) comprenant au moins un élément semi-conducteur (4), l'élément semi-conducteur (4) présentant un élément de mise en contact (18), l'élément de mise en contact (18) de l'élément semi-conducteur (4) étant relié par liaison de matière à une surface métallique (14) par l'intermédiaire d'une couche de liaison (20). Pour fabriquer un module semi-conducteur (2) de manière plus simple et plus fiable par rapport à l'état de la technique, la surface métallique (14) présente une cavité (22) dans laquelle la couche de liaison (20) est disposée, l'élément de mise en contact (18) chevauchant au moins partiellement la cavité (22).
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