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1. (WO2019005148) FLOATING GATE TRANSISTOR
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CLAIMS

We claim:

1. An apparatus comprising:

a gate disposed between a source and a drain, the gate having a length and a width, wherein the width is orthogonal to the length, wherein the length extends between the source and drain, and wherein the width extends away from the source and drain, wherein the width is greater than the length;

a first conductor extending along the width of the gate;

a second conductor extending along the width of the gate such that the first and second conductors are parallel to one another, and wherein the first and second conductors are disposed on either sides of the gate;

a third conductor coupled to the source;

a fourth conductor coupled to the drain; and

wherein the first and second conductors are disconnected from the third and fourth conductors.

2. The apparatus of claim 1, wherein the first and second conductors are coupled together.

3. The apparatus according to any one of claims 1 to 2, wherein the first, second, third, and fourth conductors comprise a same material.

4. The apparatus of claim 3, wherein the material for the first, second, third, and fourth conductors includes one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

5. The apparatus of claim 1, wherein the fourth conductor is coupled to a storage node of a memory cell.

6. The apparatus according to any one of claims 1 to 3, wherein the third conductor is

coupled to a transistor.

7. The apparatus of claim 6, wherein the transistor is coupled to a power supply node.

8. The apparatus of claim 6, wherein the transistor is controllable by a control signal.

9. An apparatus comprising:

a first transistor coupled to a power supply node;

a memory cell; and

a second transistor coupled to the memory cell and the first transistor, wherein the second transistor comprises a gate which is independent of an ohmic contact and is controlled by charging or discharging a conductor which is at least partially around the gate.

10. The apparatus of claim 9, wherein the second transistor is coupled to a storage node of the memory cell.

11. The apparatus according to any one of claims 9 to 10, wherein the second transistor

includes source and drain regions coupled to first and second conductors, respectively, wherein the first and second conductors comprise a material which is same as a material of the conductor which is at least partially around the gate of the second transistor.

12. The apparatus of claim 11, wherein the material includes one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

13. The apparatus of claim 9, wherein the memory cell is an SRAM memory bit-cell.

14. The apparatus of claim 9, wherein the memory cell is part of a data flip-lop (DFF).

15. A method comprising:

disposing a gate between a source and a drain, the gate having a length and a width, wherein the length is orthogonal to the width, wherein the length extends between the source and drain, and wherein the width extends away from the source and drain, wherein the width is greater than the length;

forming a first conductor extending along the width of the gate;

forming a second conductor extending along the width of the gate such that the first and second conductors are parallel to one another, and wherein the first and second conductors are disposed on either sides of the gate;

forming a third conductor coupled to the source; and

forming a fourth conductor coupled to the drain, wherein the first, second, third, and fourth conductors comprise a same material.

16. The method of claim 15, wherein the first and second conductors are disconnected from the third and fourth conductors.

17. The method of claim 15 comprising: coupling the first and second conductors together.

18. The method of claim 15, wherein the material for the first, second, third, and fourth

conductors include one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

19. The method of claim 15 comprises coupling the fourth conductor to a storage node of a memory cell.

20. The method according to any one of claims 15 to 19 comprises coupling the third

conductor to a transistor.

21. The method of claim 20 comprises coupling the transistor to a power supply node.

22. The method according to any one of claims 20 to 21 comprises controlling the transistor by a control signal.

23. A system comprising:

a processor;

a memory coupled to the processor, wherein the memory include an apparatus according to any one of claims 1 to 8, or any one of claims 9 to 14; and

a wireless interface to allow the processor to communicate with another device.

24. A method comprising:

forming a first transistor coupled to a power supply node;

forming a memory bit-cell; and

forming a second transistor coupled to the memory bit-cell and the first transistor, wherein the second transistor comprises a gate which is independent of an ohmic contact and is controlled by charging or discharging a conductor which is at least partially around the gate.

25. The method of claim 24 comprises:

coupling the second transistor to a storage node of the memory bit-cell; and coupling source and drain regions of the second transistor coupled to first and second conductors, respectively, wherein the first and second conductors comprise a material which is same as a material of the conductor which is at least partially around the gate of the second transistor.