Einige Inhalte dieser Anwendung sind momentan nicht verfügbar.
Wenn diese Situation weiterhin besteht, kontaktieren Sie uns bitte unterFeedback&Kontakt
1. (WO2019005129) SPIN HALL EFFECT MAGNETIC RANDOM-ACCESS MEMORY BITCELL
Anmerkung: Text basiert auf automatischer optischer Zeichenerkennung (OCR). Verwenden Sie bitte aus rechtlichen Gründen die PDF-Version.

SPIN HALL EFFECT MAGNETIC RANDOM- ACCESS MEMORY BITCELL

BACKGROUND

Embedded processor and memory designs, such as system on a chip (SoC), benefit from large embedded nonvolatile high-speed memory. Embeddable memory technologies with these or similar features include static random-access memory (SRAM), flash, resistive RAM (RRAM) and spin-transfer torque (STT) magnetoresistive RAM (STT-MRAM), to name a few. However, each of these technologies has limitations in areas like performance, density, power consumption, volatility, and fabrication compatibility that prevent them from being the clear choice over the other technologies,

BRIEF DESCRIPTION OF THE DRAWINGS FIG 1 is a top-down schematic circuit diagram of an example SHE-MRAM memory cell

(bitcell), according to an embodiment of the present disclosure.

FIG. 2 is a top-down schematic circuit diagram of an example SHE-MRAM 2 >< 4 bitcell array, according to an embodiment of the present disclosure.

FIG. 3 is a block diagram of an example SHE-MRAM including bitcell array and corresponding peripheral circuits, according to an embodiment of the present disclosure.

FIG 4 is a timing diagram of example signals for driving the bitcell of claim 1, according to an embodiment of the present disclosure.

FIGs. 5A-5F are top-down layout views of different layers that make up an example SHE-MRAM bitcell array, according to an embodiment of the present disclosure.

FIG. 6 is an example cross-sectional (X-Z) view of the bitcell array of FIGs. 5A-5F, according to an embodiment of the present disclosure.

FIG. 7 is an example cross- sectional (Y-Z) view of the bitcell array of FIGs. 5A-5F and 6, according to an embodiment of the present disclosure.

FIG. 8 is an example cross-sectional (X-Z) view of a bitcell of FIGs. 5A-5F and 6-7, according to an embodiment of the present disclosure.

FIG. 9 is an example cross-sectional (Y-Z) view of a bitcell of FIGs. 5A-5F and 6-8, according to an embodiment of the present disclosure.

FIG. 10 is a cross-sectional (Y-Z) view of an example magnetic tunnel junction (MTI), according to an embodiment of the present disclosure.

FIG. 1 1 illustrates an example method of fabricating a SFIE-MRAM bitcell, according to an embodiment of the present disclosure.

FIG. 12 illustrates an example method of fabricating a SHE-MRAM bitcell array, according to an embodiment of the present disclosure.

FIG. 13 illustrates an example method of writing a SHE-MRAM bitcell, according to an embodiment of the present disclosure.

FIG. 14 illustrates an example computing system implemented with the integrated circuit structures or techniques disclosed herein, according to an embodiment of the present disclosure.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

A two-transistor (2T), one magnetic tunnel junction (1MTJ), spin Hall effect (SHE) MRAM memory cell (bitcell) and array architecture are proposed. The proposed design enables a new class of MRAM with faster access speed than STT-MRAM, smaller bitcell area than SRAM (in addition to complete nonvolatility), and a fabrication process compatible with present fabrication techniques. It has the potential to replace on-die SRAM cache as well as forms of embedded nonvolatile memory technologies such as embedded flash and embedded RRAM in future SoC products. The proposed design further has the potential to enable embedded nonvolatile memory with the performance and dynamic power comparable to embedded SRAM while achieving higher density and complete nonvolatility. The proposed design further provides value to future SoC products that need high-speed, high performance, and nonvolatile embedded memory technology.

According to various embodiments of the present disclosure, a spin Hall effect (SHE) magnetoresistive random-access memory (MRAM) bitcell is provided. The bitcell can be fabricated using the device level (e.g., front end of line, or FEOL) and first (lowest) three metal interconnection layers of a semiconductor fabrication process, such as a complementary metal oxide semiconductor (CMOS) fabrication process. The bitcell includes first and second access transistors in a device level of a semiconductor device or integrated circuit (e.g., processor or microprocessor with embedded memory), a wordline in the device level and coupled to gate terminals of the first and second access transistors, first and second source lines in a lowest metal interconnect layer of the semiconductor device (e.g., metal 1) and coupled to source terminals of the first and second access transistors, respectively, spin Hall metal in a lower portion of a second lowest metal interconnect layer of the semiconductor device (e.g., metal 2) and coupling drain terminals of the first and second access transistors, an MTJ in an upper portion of the second lowest metal interconnect layer and having a bottom terminal coupled to the spin Hall metal, and a bitline in a third lowest metal interconnect layer of the semiconductor device (e.g., metal 3) and coupled to a top terminal of the MTJ. Example spin Hall metals include, for instance, beta tantalum (β-Ta), beta tungsten (β-W), and platinum (Pt).

According to various other embodiments, an array of SHE-MRAM bitcells is provided. The bitcell array includes wordlines in a device level of a semiconductor device and extending in a first direction, first source lines and second source lines in a lowest metal interconnect layer of the semiconductor device and extending in a second direction crossing the first direction, bitlines in a third lowest metal interconnect layer of the semiconductor device and extending in the second direction, and bitcells where the wordlines cross the first source lines, the second source lines, and the bitlines. Each of the bitcells includes first and second access transistors in the device level and having gate terminals coupled to one of the wordlines and source terminals coupled to respective ones of the first and second source lines, spin Hall metal in a lower portion of a second lowest metal interconnect layer of the semiconductor device and coupling drain terminals of the first and second access transistors, and an MTJ in an upper portion of the second lowest metal interconnect layer and having a bottom terminal coupled to the spin Hall metal and a top terminal coupled to one of the bitlines.

General Overview

According to one or more embodiments of the present disclosure, a 2T-1MTJ-SHE-MRAM bitcell uses a giant spin Hall effect (SHE) magnetic tunnel junction (MTJ) device to achieve low-energy and low-latency write operations. In one embodiment, the fabrication of an array of such bitcells uses the lowest three metal interconnect layers (e.g., metal 1, metal 2, and metal 3 layers) of a back end of line (BEOL) semiconductor fabrication process, with the three-terminal MTJ memory devices replacing the metal 2 layer in the memory array. The source lines of each bitcell use the metal 1 layer below the MTJ, while the bitline of each bitcell uses the metal 3 layer above the MTJ. The bitcell fabrication process thus uses standard logic process features, which makes it feasible to integrate SHE-MRAM in s standard logic process for embedded memory applications.

Accordingly, in some embodiments of the present disclosure, SHE-MRAM bitcell architectures are provided that use technology and design rules offered in standard logic processes, which reduces the complexity of integrating SHE-MRAM memory arrays in the logic process technology. Such bitcell architectures provide a feasible path to integrate embedded SHE-MRAM in future SoC designs. The spin Hall effect MTJ shows significant write time improvement compared to perpendicular and in-plane MTJs. According to some embodiments of the present disclosure, the proposed 2T-1MTJ-SHE-MRAM bitcell and bitcell array enables the use of SHE-MTJ devices as the data storage elements in an embedded nonvolatile RAM circuit.

System Architecture

FIG. 1 is a top-down (Y-X) schematic circuit diagram of an example SHE-MRAM memory cell 100 (bitcell), according to an embodiment of the present disclosure. FIG. 2 is a top-down (Y-X) schematic circuit diagram of an example SHE-MRAM 2 x 4 bitcell array 200, according to an embodiment of the present disclosure. For ease of presentation, in the example illustrations, the X direction is the wordline direction (or row direction) of a bitcell array (e.g., parallel to the access transistor gates, or the same direction as the access transistor gates), while the Y direction is the source line and bitline direction (or column direction, e.g., orthogonal to the access transistor gates, or perpendicular to access transistor gate direction) and the Z direction is the vertical direction (e.g., from the substrate and FEOL or device level upwards to the lower metal interconnection layers and then higher metal interconnection layers of the BEOL of a semiconductor fabrication process). In addition, as illustrated and discussed throughout, an n-channel field-effect transistor (FET), such as an nMOS transistor-based embedded memory is shown and described, but other embodiments are not so limited, and may use a different logic process (such as pMOS), as would be apparent in light of the present disclosure.

FIG. 1 depicts the schematics of a 2T-1MTJ-SHE-MRAM bitcell 100 (two-transistor, one

MTJ) while FIG. 2 depicts the schematics of a 2 χ 4 array 200 made of such SHE-MRAM bitcells 100. Each bitcell 100 is a two-state device (e.g., 0 or 1), and includes two access (or select or selector) transistors (access transistor A 1 10 and access transistor B 120, or access A and access B), a three terminal SHE-MTJ device 140, SHE electrode (spin Hall metal) 130, a

wordline 150 (e.g., row selector), source line A 170 and source line B 180, and a bitline 160 (e.g., column selector, in conjunction with the source lines 170 and 180). In the bitcell array 200, each bitcell 100 is at a corresponding crossing region formed by one of the wordlines 150 together with one of the A source lines 170, one of the B source lines 180, and one of the bitlines 160. Each of the bitlines 160, A source lines 170, B source lines 180 are shared among bitcells 100 oriented in the Y (e.g., orthogonal to access transistor gate) direction. Each of the wordlines 150 is shared among bitcells 100 oriented in the X (e.g., parallel to access transistor gate) direction. The bitcell array 200 may be driven by other circuits, such as sense amplifiers, wordline drivers, source line drivers, and bitline drivers. These other circuits may be located, for example, at a periphery of the bitcell array 200.

In further detail, access transistor A 1 10 includes a gate electrode A 116 coupled to (e.g., electrically connected to) the wordline 150, a source electrode A 112 coupled to source line A 170, and a drain electrode A 114 coupled to the spin Hall metal 130. Likewise, access transistor B 120 includes a gate electrode B 126 coupled to the wordline 150, a source electrode B 122 coupled to source line B 180, and a drain electrode B 124 coupled to the spin Hall metal 130. The MTJ 140, together with the spin Hall metal 130, forms a three-terminal SHE-MTJ device 140, with a first terminal coupled to the bitline 160, a second terminal coupled to the drain electrode A 114 for defining a current path between the bitline 160 and source line A 170 (via access transistor A 110), and a third terminal coupled to the drain electrode B 124 for defining a current path between the bitline 160 and source line B 180 (via access transistor B 120).

In some embodiments, the bitcell 100 includes only two transistors (i.e., access transistor A 110 and access transistor B 120). In some embodiments, the bitcell 100 includes only one MTJ (e.g., the MTJ 140).

FIG. 3 is a block diagram of an example SHE-MRAM 300 including bitcell array 200 and corresponding peripheral circuits 310-350, according to an embodiment of the present disclosure. The peripheral circuits include a row (or wordline) driver 310 for addressing or driving rows of memory cells in the bitcell array 200, a column (or source line and bitline) driver 320 for addressing or driving columns of memory cells in the bitcell array 200, a read driver 340 (such as sense amplifier circuits) for reading states (e.g., high state and low state, or spin-up or spin-down) of the individual bitcells that make up the bitcell array 200, a write driver 330 for writing states of the individual bitcells that make up the bitcell array 200, and a customizing circuit 350 for adjusting values (e.g., voltage values, pulse durations, and the like) of parameters that control the read driver 340 and the write driver 330. For example, the customizing circuit 350 can be used to reduce or minimize the write error rate by adjusting voltage values of the

bitlines and driving periods of the source lines and bitlines to reduce or minimize the occurrence of errors during the writing process.

FIG. 4 is a timing diagram of example signals 400 for driving the bitcell 100 of claim 1, according to an embodiment of the present disclosure. The signals 400 include supply voltages of the wordline 150, source line A 170, source line B 180, and bitline 160 during bitcell 100 write and read operations. The signals are illustrated as voltages over time (time advancing from left to right), with 0V representing the low (or ground) voltage and VCC representing the high voltage. The write operation is enabled by turning on both access transistors A and B of the bitcell 100 at the same time, as represented by the high voltage 410 for the wordline 150 (during periods Tl and T2). During this time, voltages with opposite polarity are supplied to source lines A and B to create current flowing through the SHE electrode (spin Hall metal) 130, as represented by the high voltage 420 for source line A 170 (and low voltage for source line B 180) during the first half of the high voltage 410 for the wordline 150 (period Tl), and the high voltage 430 source line B 180 (and low voltage for source line A 170) during the second half of the high voltage 410 for the wordline 150 (period T2).

The direction of the write current along the SHE electrode 130 produces a spin injection current, which alters magnetization of the free layer (e.g., spin up or spin down) in the MTJ 140 above, resulting in a change of the MTJ resistance (and corresponding change in state of the MTJ 140). To write such an MTJ 140 with perpendicular anisotropy, source line A 170, source line B 180, and bitline 160 are biased in a four-part sequence to reduce or minimize write error rate, as shown in FIG. 4 (using, for example, the components of the SHE-MRAM 300 of FIG. 3). The four parts include periods Tl (when the source line A voltage 420 is asserted), T2 (when the source line B voltage 430 is asserted), and T3 (when a particular voltage 445, such as a tunable or programmable voltage, is supplied to the bitline 160 during the interval 440). Period T3 has two portions, including a first (or overlapping) portion 435 that overlaps with period T2 when the source line B voltage 430 is asserted, and a second (or following) portion when neither the source line A voltage 420 nor the source line B voltage 430 is asserted. During periods Tl and T2, the source line voltage switches polarity between source line A 170 and source line B 180. During the overlap portion 435 of periods T2 and T3, the bitline 160 is biased at an appropriate voltage 445 (such as a programmable voltage) to provide additional current through the MTJ 140 to help reduce or minimize the write error rate.

In one or more embodiments, the timing of asserting the bitline voltage 445 (portion 435 of periods T2 and T3) relative to the initial portion of period T2 (when only the source line B voltage 430 is asserted) is a programmable quantity, as is the magnitude of the asserted bitline voltage 445 (e.g., a first bitline voltage 445 or write bitline voltage 445, asserted during period 440). Accordingly, the overlap portion 435 and the write (or first) bitline voltage 445 can be programmed to achieve an improved or optimal write error rate (using, for example, the customizing circuit 350 of FIG. 3).

It should be noted that the described write operation imparts one state to the MTJ 140 (such as spin up or spin down). The other state can be written to the MTJ with the same procedure, only reversing the roles of source line A 170 and source line B 180 (e.g., first assert voltage 420 in source line B 180 during period Tl, then assert voltage 430 in source line A 170 during period T2).

Still referring to FIG. 4, the read operation is illustrated to the right of the write operation. During the read operation, source line A 170 and source line B 180 are biased at ground voltage (e.g., while the wordline 150 is set to high voltage 460). According to one or more embodiments, sense amplifier circuitry outside of the memory array biases the bitline 160 to another voltage level 455 (e.g., during period 450 that encompasses period 460 when the access transistors are switched on with their source voltages biased to ground). This other voltage level 455, such as another programmable voltage level (e.g., a second bitline voltage 455 or read bitline voltage 455) can be the same or different than the first (or write) bitline voltage 445. By using an appropriate second (or read) bitline voltage 455, the sense amplifier circuitry can further determine the magnitude of the current flowing from the bitline 160 through the MTJ 140 to the source lines 170 and 180 to achieve a good or optimal margin of reading the correct resistance level (e.g., state of the memory device, such as 0 or 1) from the MTJ 140.

FIGs. 5A-5F are top-down (Y-X) layout views of different layers that make up an example SHE-MRAM bitcell array 595, according to an embodiment of the present disclosure. Throughout these illustrations, and some of the figures that follow, portions of a bitcell array 595 are illustrated, together with dashed regions delineating corresponding portions of a single bitcell 500 as well as of an access transistor A (access A) 550 and an access transistor B (access B) 555 that make up a single bitcell 500. In FIGs. 5A-5E, it should be noted that, together, the access A 550 and access B 555 portions (on the right-hand side of the drawings) make up a single bitcell 500 that is separate and distinct from the bitcell 500 delineated on the left-hand side of the drawings. The drawings are not done to any particular scale, and the bitcell array 595, bitcell 500, access transistor A 550, and access transistor B 555 are shown primarily for illustrative purposes, and not for purposes of limitation.

FIGs. 5A-5F show top-down schematic views (at different layers) of a 2T-1MTJ-SUE-MRAM bitcell array 595. Each of the bitcells 500 includes two access transistors (2T) and one MTJ (1MTJ). The layouts in FIGs. 5A-5F are drawn at different levels or layers during a sample semiconductor fabrication process (such as an nMOS fabrication process), including the

transistor or device level (FEOL, FIGs. 5A-5B), the lowest or first metal interconnection layer (metal 1, FIG. 5C), the second lowest or second metal interconnection layer (metal 2, FIGs. 5D-5E), and the third lowest or third metal interconnection layer (metal 3, FIG. 5F). For instance, the semiconductor fabrication process may be a 32 nanometer (nm) process, or may be directed to a smaller feature size technology, such as 22 nm, 14 nm, 10 nm, 7 nm, 5 nm, and beyond. In general, the features of the current layer are visible in FIGs. 5A-5F, together with the features of any earlier layer that are not obscured by the current layer (or layer more recent than the earlier layer).

In short, FIG. 5A shows the SHE-MRAM bitcell array 595 at the transistor level (first part of FEOL), FIG. 5B shows the bitcell array 595 at the diffusion contact level (second part of FEOL), FIG. 5C shows the metal 1 layer (source lines and drain electrodes), FIG. 5D shows the lower portion of the (customized) metal 2 layer (spin Hall metal electrodes and drain vias), FIG. 5E shows the upper portion of the (customized) metal 2 layer (MTIs), and FIG. 5F shows the metal 3 layer (bitlines and MTJ vias). The metal 2 layer is customized in a sense that unlike the normal metal 2 interconnection layer used to fabricate the remainder of the semiconductor device (or integrated circuit) in which the bitcell array 595 is embedded, the same area and vertical space in the metal 2 layer for the bitcell array 595 is instead used to form the spin Hall metal electrodes and MTJs. The metal 1 and metal 3 layers, by contrast, are used in a manner similar to the remainder of the semiconductor device, interconnecting features via horizontal wires and contacts in the immediately lower levels (such as transmitting signals horizontally to source and drain diffusion contacts or to MTJs via structures such as source lines, drain electrodes, or bitlines).

In FIGs. 5A-5F, the bitcell dimension is two times the gate pitch in the Y direction (or orthogonal-to-transistor-gate direction) and four times the Ml (metal 1) pitch in the X direction (or parallel-to-transistor-gate direction), as can be seen more clearly in FIGs. 5A-5C. See, for example, two gate electrodes in the width (Y) direction of the bitcell 500 in the device level (FEOL) drawing of FIG. 5B, and four features (two source lines and two drain electrodes) in the length (X) direction of the bitcell 500 in the metal 1 layer drawing of FIG. 5C. The transistor gates 520 of access transistor A 550 and access transistor B 555 can be connected to the same metal wordline at a wordline driver outside of the memory array 595. Both source line A 540 and source line B 545 in each bitcell 500 use metal 1, as shown in Fig. 5C, as do the corresponding drain electrodes, drain electrode A (drain A) 560 and drain electrode B (drain B) 565, of each of the access transistors. In FIGs. 5D-5E (metal 2), spin Hall metal electrode 570 (where MTJ 580 lands) connects to the two corresponding drains 560 and 565 using shallow drain vias filled with metal stubs. The MTJ 580 lands on the SHE electrode 570 and is equally spaced between the two

shallow vias (drain vias) and metal stubs below the SHE electrode 570. The dimension and thickness of the SHE electrode 570 can be improved or optimized to achieve high spin injection into the MTJ 580. In FIG. 5F (metal 3), the MTJ 580 is connected to a bitline 590 using a via in the metal 3 layer.

FIG. 6 is an example cross-sectional (X-Z) view of the bitcell array 595 of FIGs. 5A-5F, according to an embodiment of the present disclosure. FIG. 7 is an example cross-sectional (Y-Z) view of the bitcell array 595 of FIGs. 5A-5F and 6, according to an embodiment of the present disclosure. FIG. 8 is an example cross-sectional (X-Z) view of a bitcell 500 of FIGs. 5A-5F and 6-7, according to an embodiment of the present disclosure. FIG. 9 is an example cross-sectional (Y-Z) view of a bitcell 500 of FIGs. 5A-5F and 6-8, according to an embodiment of the present disclosure. FIGs. 6-9 depict cross-sectional schematics of bitcells 500 and bitcell arrays 595 of a 2T-1MTJ-SHE-MRAM design in X (parallel to access transistor gate) and Y (orthogonal to access transistor gate) directions. Each bitcell 500 uses a device level 810 (e.g., FEOL) and three metal layers (e.g., the three lowest metal interconnection layers of a semiconductor fabrication process, such as the first three metal layers of the BEOL, as in a first metal layer (metal 1) 820, a second metal layer (metal 2) 830, and a third metal layer (metal 3) 840). The MTJ 580 and SHE electrode (spin Hall metal) 570 replace the metal 2 layer (e.g., customized metal 2 layer in the SHE-MRAM array 595 of the semiconductor device in which the array 595 is embedded). Both source lines 540 and 545 in each bitcell 500 are below the SHE electrode 570.

In further detail, in FIG. 5A, the first part of the FEOL process is illustrated. The process begins with a substrate 505 (see FIGs. 6-9), such as a p-type substrate (e.g., silicon (Si) doped with p-type impurities) or a silicon on insulator (SOI) substrate, on which may be fins (e.g., silicon fins; see, for example, diffusion fins 535 in FIGs. 6 and 8) defining the transistor channel regions (e.g., using FinFET technology). The channel regions are semi -conductive, as controlled by a gate signal supplied by the wordlines 525. On the substrate 505, gate electrode material (e.g., layers of insulating and conducting materials) are formed, such as through photolithography, into strips extending in the X direction and identified as poly 510 in the drawings.

In general, photolithography may be used for any of the layers and features in the fabrication process. The first layer of the poly 510 may be a gate dielectric layer. The gate dielectric can be silicon dioxide (Si02), silicon nitride (e.g., Si3N4), hafnium dioxide (Hf02) or other high-K material, or a multi -layer stack including a first layer of Si02 and a second layer of a high-K dielectric such as Hf02 on the Si02 Any number of gate dielectrics can be used, as will be appreciated in light of the present disclosure. For example, in one embodiment, the gate

dielectric is a layer of Si02. In another embodiment, the gate dielectric is a stack (e.g., two or more layers) of Hf02 on Si02. Above the gate dielectric, a conductive material is formed, such as highly doped polysilicon or two or more conductive layers such as highly doped polysilicon on top of a thin layer of metal (such as tungsten (W) or aluminum (Al)) or a silicide (such as TiSi, MoSi, TaSi or WSi).

After the gate electrode material (poly 510) has been formed, diffusion areas 515 and 518 (such as n-type diffusion areas) are formed through, for example, diffusion or ion implantation of n-type material at areas corresponding to the active areas of access transistor A (or access A) 550 and access transistor B (or access B) 555. These active areas, namely source diffusion 515 and drain diffusion 518, correspond to the source regions and the drain regions, respectively, of the access transistors. The corresponding areas of the poly 510 become the gate electrodes 520. Pairs of poly lines 510 function as a wordline 525, each access transistor being formed from two gate electrodes 520 (driven by a different poly line 510 of the same wordline 525) and two corresponding channel regions beneath the gate electrodes 520. For example, each access transistor can be a multigate device, as with FinFET technology), coupling corresponding source regions to a single (common) drain region. In some embodiments, the two poly 510 lines that make up each wordline 525 are driven by a common source, such as by a metal wordline from a wordline driver at a periphery of the bitcell array 595. In other embodiments, each poly 510 that makes up a wordline 525 is driven independently.

In addition, as illustrated in FIG. 5B, diffusion contact material (conductive material, such as metal, e.g., Al or W) is formed over the diffusion areas 515 and 518 (including diffusion fins 535) corresponding to the source and drain regions, respectively, to form source diffusion contacts 530 and drain diffusion contacts 533. The source diffusion contacts 530 and drain diffusion contacts 533 allow electrical connection between the source and drain regions below and metal interconnection features above. It should be noted that adjacent bitcells 500 in the Y direction share a common source diffusion contact 530 and a common source diffusion 515 for each of access transistor A 550 and access transistor B 555.

In FIGs. 5C-5F, the BEOL portion of the bitcell array 595 is illustrated, specifically the first three metal interconnect layers (e.g., metal 1, metal 2, and metal 3). Generally speaking, each of the metal interconnect layers includes a pattern of conductive metal, such as copper (Cu) or aluminum (Al) formed in a dielectric medium or inter-layer dielectric (ILD), such as by photolithography.

In FIG. 5C, the metal 1 layer (e.g., lowest metal interconnection layer of the BEOL) is formed. The metal 1 layer (or any of the BEOL metal interconnection layers) can be, for example, copper (Cu), Al, or W. Prior to forming the metal 1 layer, the surface of the FEOL

portion is insulated and planarized, such as with a dielectric material (e.g., a sealing or etch stop material, such as silicon carbide (SiC)), and diffusion contact vias formed in the dielectric material to expose the diffusion contacts 530 and 533. In the X direction, the diffusion contacts 530 or 533 correspond to either the source regions or the drain regions, while in the Y direction, the diffusion contacts 530 and 533 alternate between the source regions and the drain regions.

The diffusion contact vias are offset in the Y direction to allow the source lines 540 and 545 to be formed adequately separated from the drain electrodes 560 and 565, the source lines 540 and 545 being formed over the source region diffusion contact vias and the drain electrodes 560 and 565 being formed over the drain region diffusion contact vias. Each source line, such as source line A 540 or source line B 545, is commonly coupled (e.g., electrically connected) to each of the source diffusion contacts 530 in the Y direction while each drain electrode, such as drain A 560 or drain B 565, is coupled to only a single drain diffusion contact 533. The source lines 540 and 545 extend fully (e.g., between the bitcells 500) in the Y direction while the drain electrodes 560 and 565 extend partially (e.g., within the bitcells 500) in the Y direction.

In FIGs. 5D-5E, the metal 2 layer (e.g., second lowest metal interconnection layer of the

BEOL) is customized for the bitcell array 595 (versus the rest of the semiconductor device). In place of the metal 2 interconnect and vias (as may be used in the remainder of the semiconductor device), in the bitcell array 595, in a lower portion of the metal 2 layer, spin Hall metal 570 is formed, while in an upper portion of the metal 2 layer, an MTJ 580 is formed. For example, the same technique (e.g., SiC etch stop, vias or other through-holes to expose lower features, one or more metal layers, and the like) may be used in each of the different portions. Together, the lower and upper portions of the metal 2 layer may take up the same space as the metal 2 layer in the rest of the semiconductor device, so that the metal 3 layer can use a common process for the entire semiconductor device.

In FIG. 5D, a lower portion of the metal 2 layer is formed in the bitcell array 595. It includes drain vias (such as relatively shallow drain vias in a lowest portion of the metal 2 layer) for the corresponding drain A 560 and drain B 565 electrodes below. The drain vias can be filled, for example, with non-magnetic conductive material, such as metal stubs made of non-magnetic or paramagnetic metal (e.g., Al or Cu). A layer of spin Hall metal 570 connects the corresponding drain A 560 and drain B 565 electrodes in the same bitcell, forming a spin Hall effect or SHE electrode 570, e.g., formed on top of the drain via metal. The SHE electrode 570 also serves as a write electrode. The SHE electrode 570 exhibits the spin Hall effect. The spin Hall effect is characterized by spin accumulation in the lateral boundaries (or sides) of a current-carrying conductor. The directions of the spins are opposite at the two sides, and they reverse directions if the current is reversed. The spin Hall effect (or spin accumulation) takes place

without a magnetic field. For example, the SHE electrode 570 may include beta tantalum (β-Ta), beta tungsten (β-W), or platinum (Pt), to name a few.

In FIG. 5E, an upper portion of the metal 2 layer is formed in the bitcell array 595. This includes forming an MTJ 580 on the spin Hall metal 570, such as equidistant from the metal stubs that fill the two drain vias on either end of spin Hall metal 570, and overlapping the source line B 545 below (e.g., in a vertical direction). FIG. 10 is a cross-sectional (Y-Z) view of an example MTJ 580, according to an embodiment of the present disclosure. The MTJ 580 may be fabricated in a series of layers, such as thin-film layers including a bottom magnet or free magnet 581 (e.g., a free polarity or free-spin or free spin orientation magnet of ferromagnetic material, having a majority of electrons of the same spin), a thin insulator or tunnel barrier 583 (e.g., at most a few nanometers (nm) thick, such as magnesium oxide (MgO), to allow tunneling by electrons), a top magnet or fixed magnet 585 (e.g., a fixed polarity or fixed-spin or fixed spin orientation magnet of ferromagnetic material), an anti-ferromagnetic layer 587 (e.g., devoid of magnetization, to help preserve the fixed magnet 585 from reorienting to a different magnetic alignment, and made of materials such as ruthenium (Ru) or tantalum (Ta)), and a top electrode 589 (e.g., conductive metal). In some embodiments, the anti-ferromagnetic layer 587 is not present. In some embodiments, the fixed magnet 585 is thicker than (such as more than twice as thick as) the free magnet 581.

The fixed magnet 585 has electrons of one spin (fixed) while the free magnet can switch between electrons having the same spin as the fixed magnet 585 and electrons having the opposite spin (e.g., through a dynamic write process, such as that described above with reference to FIG. 3). In some embodiments, the fixed magnet 585 is one or more layers of cobalt (Co), cobalt-platinum (Pt) alloys, ruthenium (Ru), cobalt-iron (CoFe) alloys, cobalt-iron-boron (CoFeB) alloys, and tungsten (W). In one or more embodiments, the tunnel barrier 583 is magnesium oxide (MgO). In some embodiments, the free magnet 581 is CoFeB alloys. In another embodiment, the free magnet 581 is tungsten (W). In another embodiment, the free magnet 581 is tantalum (Ta). The top electrode 589 can also serve as a protective surface for receiving metal from the metal 3 layer above (through the MTJ via). The top electrode can be a thin layer of metal or other conductive material (e.g., tantalum nitride (TaN), titanium nitride (TiN), and tantalum (Ta), to name a few). The top electrodes 589 of the MTJs 580 of the same bitline 590 are electrically connected to each other, such as through the MTJ vias connecting the top electrodes 589 to the bitline 590.

In FIG. 5F, the metal 3 layer is formed in the bitcell array 595. This includes forming MTJ vias corresponding to the MTJs 580, and forming bitlines 590 parallel to the source lines 540 and 545 (e.g., extending in the Y direction). The metal 3 layer can be formed, for example, of

conductive metal, such as Al or Cu. Each bitline 590 can be commonly coupled to the bitcells 500 in the Y direction (e.g., through their corresponding MTJs 580.

Methodology

FIG. 1 1 illustrates an example method 1100 of fabricating a SHE-MRAM bitcell (such as bitcell 100 of FIGs. 1-2), according to an embodiment of the present disclosure. FIG. 12 illustrates an example method 1200 of fabricating a SHE-MRAM bitcell array (such as bitcell array 200 of FIG. 2) including bitcells where wordlines cross first source lines, second source lines, and bitlines, according to an embodiment of the present disclosure. These and other methods disclosed herein may be carried out using integrated circuit fabrication techniques such as photolithography as would be apparent in light of the present disclosure. The corresponding SHE-MRAM bitcell and SHE-MRAM bitcell array may be part of other (logic) devices on the same substrate, such as application specific integrated circuits (ASICs), microprocessors, central processing units, processing cores, and the like. Unless otherwise described herein, verbs such as "coupled" or "couple" refer to an electrical coupling (such as capable of transmitting an electrical signal, e.g., electrically connected), either directly or indirectly (such as through one or more conductive layers in between).

Referring to FIGs. 11-12 (with specific example references to the structures of FIGs. 1-10) method 1 100 includes forming 1110 first and second access transistors (such as access transistor A 110 and access transistor B 120) on a substrate in a device level of a semiconductor device. (e.g., a microprocessor with embedded memory), such as a FEOL process. Method 1100 further includes forming 1120 a wordline (such as wordline 150) in the device level and coupled to gate terminals (such as gate electrode A 1 16 and gate electrode B 126) of the first and second access transistors. Method 1 100 further includes forming 1 130 a first source line (such as source line A 170) and a second source line (such as source line B 180) in a lowest metal interconnect layer (such as metal 1 in the BEOL) of the semiconductor device and coupled to source terminals (such as source electrode A 1 12 and source electrode B 122) of the first and second access transistors, respectively.

Method 1 100 further includes forming 1140 spin Hall metal (such as spin Hall metal 130) in a lower portion of a second lowest metal interconnect layer (such as metal 2) of the semiconductor device, the spin Hall metal coupling drain terminals (such as drain electrode A 114 and drain electrode B 124) of the first and second access transistors. Method 1 100 further includes forming 1150 a magnetic tunnel junction (MTJ, such as MTJ 140) in an upper portion of the second lowest metal interconnect layer, the MTJ having a bottom terminal coupled to the spin Hall metal. Method 1100 further includes forming 1 160 a bitline (such as bitline 160) in a

third lowest metal interconnect layer (such as metal 3) of the semiconductor device and coupled to a top terminal of the MTJ.

Method 1200 includes forming 1210 the wordlines (such as wordlines 525) on a substrate (such as substrate 505) in a device level of a semiconductor device, the wordlines extending in a first direction (such as the X direction). Method 1200 further includes, for each bitcell (such as bitcell 500), forming 1220 first and second access transistors (such as access transistor A 550 and access transistor B 555) in the device level, the first and second access transistors having gate terminals (such as gate electrodes 520) coupled to one of the wordlines. Method 1200 further includes forming 1230 the first source lines and the second source lines (such as source line A 540 and source line B 545) in a lowest metal interconnect layer of the semiconductor device, the first and second source lines extending in a second direction (such as the Y direction) crossing the first direction, each first access transistor being coupled to one of the first source lines and each second access transistor being coupled to one of the second source lines.

Method 1200 further includes, for each bitcell, forming 1240 spin Hall metal (such as spin Hall metal 570) in a lower portion of a second lowest metal interconnect layer of the semiconductor device, the spin Hall metal coupling drain terminals (such as drain A 560 and drain B 565) of the first and second access transistors. Method 1200 further includes, for each bitcell, forming 1250 a magnetic tunnel junction (MTJ, such as MTJ 580) in an upper portion of the second lowest metal interconnect layer, the MTJ having a bottom terminal (such as free magnet 581) coupled to the spin Hall metal. Method 1200 further includes forming 1260 the bitlines (such as bitlines 590) in a third lowest metal interconnect layer of the semiconductor device, the bitlines extending in the second direction, each MTJ having a top terminal (such as top electrode 589) coupled to one of the bitlines.

FIG. 13 illustrates an example method 1300 of writing a SHE-MRAM bitcell (such as bitcell 100 of FIGs 1-2), according to an embodiment of the present disclosure Here, the SHE-MRAM includes a SHE-MRAM bitcell array (such as bitcell array 200 of FIGS. 2-3) including wordlines extending in a first direction, first source lines and second source lines extending in a second direction crossing the first direction, bitlines extending in the second direction, and bitcells where the wordlines cross the first source lines, the second source lines, and the bitlines. Each bitcell includes first and second access transistors having gate terminals coupled to one of the wordlines and source terminals coupled to respective ones of the first and second source lines, spin Hall metal coupling drain terminals of the first and second access transistors, and a magnetic tunnel junction (MTJ) having a bottom terminal coupled to the spin Hall metal and a top terminal coupled to one of the bitlines. The writing of the bitcell may use, for example, the write driver 330 of FIG. 3.

Referring to FIG. 13, method 1300 includes writing data of a first state (e.g., spin up) to one of the bitcells. More specifically, method 1300 includes driving 1310 the one of the wordlines for a first period to turn on the first and second access transistors while supplying voltage of a first polarity to the first source line and supplying voltage of a second polarity opposite the first polarity to the second source line. Method 1300 further includes driving 1320 the one of the wordlines for a second period following the first period (again, turning on the first and second access transistors in the process) while supplying the second polarity voltage to the first source line and supplying the first polarity voltage to the second source line, Method 1300 further includes supplying a first voltage to the one of the bitlines for a third period overlapping and following the second period and while not driving the one of the wordlines (to turn off the first and second access transistors) during the following portion of the third period.

While the above example methods appear as a series of operations or stages, it is to be understood that there is no required order to the operations or stages unless specifically indicated. For example, in one embodiment of the method 1200, the forming 1210 of the wordlines can take place as part of or concurrently with the forming 1220 of the first and second access transistors.

Example System

FIG 14 illustrates a computing system 1400 implemented with the integrated circuit structures or techniques disclosed herein, according to an embodiment of the present disclosure. As can be seen, the computing system 1400 houses a motherboard 1402. The motherboard 1402 may include a number of components, including, but not limited to, a processor 1404 (including SHE-MRAM) and at least one communication chip 1406, each of which can be physically and electrically coupled to the motherboard 1402, or otherwise integrated therein. As will be appreciated, the motherboard 1402 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1400, to name a few examples.

Depending on its applications, computing system 1400 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1402. These other components may include, but are not limited to, volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM), resistive random-access memory (RRAM), and the like), a graphics processor, a digital signal processor, a crypto (or cryptographic) processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage

device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1400 may include one or more integrated circuit structures or devices (e.g., one or more SHE-MRAM memory cells) formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1406 can be part of or otherwise integrated into the processor 1404).

The communication chip 1406 enables wireless communications for the transfer of data to and from the computing system 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, and the like, that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1406 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1400 may include a plurality of communication chips 1406. For instance, a first communication chip 1406 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1406 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1404 of the computing system 1400 includes an integrated circuit die packaged within the processor 1404. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices (e.g., one or more SHE-MRAM memory cells) formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1406 also may include an integrated circuit die packaged within the communication chip 1406. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices (e.g., one or more SHE-MRAM memory cells) formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi- standard wireless capability may be integrated directly into the processor 1404 (e.g., where functionality of any chips 1406 is integrated into processor 1404, rather than having separate communication chips). Further note that processor 1404 may be a chip set having such wireless capability. In short, any number of processor 1404 and/or communication chips 1406 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing device 1400 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices (e.g., one or more SHE-MRAM memory cells) formed using the disclosed techniques, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is a semiconductor device including a spin Hall effect (SITE) magnetoresi stive random-access memory (MRAM) bitcell. The device includes: first and second access transistors in a device level of the semiconductor device; a wordline in the device level and coupled to gate terminals of the first and second access transistors; a first source line and a second source line in a lowest metal interconnect layer of the semiconductor device and coupled to source terminals of the first and second access transistors, respectively; spin Hall metal in a lower portion of a second lowest metal interconnect layer of the semiconductor device and coupling drain terminals of the first and second access transistors; a magnetic tunnel junction (MTJ) in an upper portion of the second lowest metal interconnect layer and having a bottom terminal coupled to the spin Hall metal; and a bitline in a third lowest metal interconnect layer of the semiconductor device and coupled to a top terminal of the MTJ.

Example 2 includes the subject matter of Example 1, where the bitcell includes only two transistors and one MTJ.

Example 3 includes the subject matter of any of Examples 1-2, where each of the first and second access transistors includes two gate electrodes for coupling two corresponding source regions to a single drain region.

Example 4 includes the subject matter of Example 3, where the wordline includes two corresponding wordlines respectively coupled to the two gate electrodes of each of the first and second access transistors.

Example 5 includes the subject matter of any of Examples 3-4, where each of the first and second access transistors further includes: two corresponding source contacts coupling the two corresponding source regions to a respective one of the first and second source lines; and a drain contact coupling the drain region to the drain terminal of a respective one of the first and second access transistors.

Example 6 includes the subject matter of any of Examples 1-5, further including first and second metal stubs in a lowest portion of the second lowest metal interconnect layer, the first and second metal stubs respectively coupling the drain terminals of the first and second access transistors to the spin Hall metal.

Example 7 includes the subject matter of Example 6, where the MTJ is equidistant to the first and second metal stubs.

Example 8 includes the subject matter of any of Examples 1-7, where the MTJ includes: a free magnet coupled to the spin Hall metal; a fixed magnet coupled to the bitline; and a tunnel barrier separating the free magnet and the fixed magnet.

Example 9 includes the subject matter of any of Examples 1-8, where the MTJ overlaps one of the first and second source lines in a vertical direction.

Example 10 includes the subject matter of any of Examples 1-9, where the spin Hall metal includes one or more of beta tantalum (β-Ta), beta tungsten (β-W), and platinum (Pt).

Example 1 1 includes the subject matter of any of Examples 1-10, where the semiconductor device is a microprocessor and the bitcell is an embedded memory cell of the microprocessor.

Example 12 includes the subject matter of any of Examples 1-11, further including a write driver to write data of a first state to the bitcell by: driving the wordline for a first period to turn on the first and second access transistors while supplying voltage of a first polarity to the first source line and supplying voltage of a second polarity opposite the first polarity to the second source line; driving the wordline for a second period following the first period while supplying the second polarity voltage to the first source line and supplying the first polarity voltage to the second source line; and supplying a first voltage to the bitline for a third period overlapping and following the second period and while not driving the wordline during the following portion of the third period.

Example 13 includes the subject matter of Example 12, further including a customizing circuit to adjust a level of the first voltage and a length of the overlapping portion of the third period.

Example 14 includes the subject matter of any of Examples 12-13, where the write driver is further to write data of a second state opposite the first state to the bitcell by: driving the wordline for the first period while supplying the second polarity voltage to the first source line and supplying the first polarity voltage to the second source line; driving the wordline for the second period while supplying the first polarity voltage to the first source line and supplying the second polarity voltage to the second source line; and supplying the first voltage to the bitline for the third period while not driving the wordline during the following portion of the third period.

Example 15 includes the subject matter of any of Examples 1-14, further including: wordlines in the device level, extending in a first direction, and including the wordline; first source lines and second source lines in the lowest metal interconnect layer, extending in a second direction crossing the first direction, the first source lines including the first source line and the second source lines including the second source line; bitlines in the third lowest metal interconnect layer, extending in the second direction, and including the bitline; and bitcells where the wordlines cross the first source lines, the second source lines, and the bitlines, the bitcells including the bitcell, each of the bitcells being configured as in the bitcell with one of the wordlines being the wordline, one of the first source lines being the first source line, one of the second source lines being the second source line, and one of the bitlines being the bitline.

Example 16 includes the subj ect matter of Example 15, where for each of the bitcells, each of the first and second access transistors includes: two gate electrodes for coupling two corresponding source regions to a single drain region; and two corresponding source contacts coupling the two corresponding source regions to a respective one of the first and second source lines, and each of the first and second access transistors of adjacent ones of the bitcells in the second direction share a common said source region and a common said corresponding source contact.

Example 17 includes the subject matter of any of Examples 15-16, where the semiconductor device is a microprocessor and the bitcells are an embedded memory cell array of the microprocessor.

Example 18 is a spin Hall effect (SHE) magnetoresistive random-access memory (MRAM) including: a SHE-MRAM bitcell array including wordlines extending in a first direction, first source lines and second source lines extending in a second direction crossing the first direction, bitlines extending in the second direction, and bitcells where the wordlines cross the first source lines, the second source lines, and the bitlines, each bitcell including first and second access transistors having gate terminals coupled to one of the wordlines and source terminals coupled to respective ones of the first and second source lines, spin Hall metal coupling drain terminals of the first and second access transistors, and a magnetic tunnel junction (MTJ) having a bottom terminal coupled to the spin Hall metal and a top terminal coupled to one of the bitlines; and a write driver to write data of a first state to one of the bitcells by driving the one of the wordlines for a first period to turn on the first and second access transistors while supplying voltage of a first polarity to the first source line and supplying voltage of a second polarity opposite the first polarity to the second source line, driving the one of the wordlines for a second period following the first period while supplying the second polarity voltage to the first source line and supplying the first polarity voltage to the second source line, and supplying a first voltage to the one of the bitlines for a third period overlapping and following the second period and while not driving the one of the wordlines during the following portion of the third period.

Example 19 includes the subject matter of Example 18, further including a customizing circuit to adjust a level of the first voltage and a length of the overlapping portion of the third period.

Example 20 includes the subject matter of Example 1 , where the customizing circuit is further to adjust lengths of the first and second periods.

Example 21 includes the subject matter of any of Examples 19-20, where the customizing circuit is further to adjust a length of the following portion of the third period.

Example 22 includes the subject matter of any of Examples 18-21, where the write driver is further to write data of a second state opposite the first state to the one of the bitcells by: driving the one of the wordlines for the first period while supplying the second polarity voltage to the first source line and supplying the first polarity voltage to the second source line; driving the one of the wordlines for the second period while supplying the first polarity voltage to the first source line and supplying the second polarity voltage to the second source line; and supplying the first voltage to the one of the bitlines for the third period while not driving the one of the wordlines during the following portion of the third period.

Example 23 includes the subject matter of any of Examples 18-22, further including a read driver to read data from the one of the bitcells by driving the one of the wordlines while supplying the second polarity voltage to the first and second source lines and while supplying a second voltage to the one of the bitlines.

Example 24 includes the subject matter of Example 23, further including a customizing circuit to adjust a level of the second voltage.

Example 25 includes the subject matter of any of Examples 23-24, where the second voltage is different than the first voltage.

Example 26 is a semiconductor device including a spin Hall effect (SHE) magnetoresi stive random-access memory (MRAM) bitcell array, the device including: wordlines in a device level of the semiconductor device and extending in a first direction; first source lines and second source lines in a lowest metal interconnect layer of the semiconductor device and extending in a second direction crossing the first direction; bitlines in a third lowest metal interconnect layer of the semiconductor device and extending in the second direction; and bitcells where the wordlines cross the first source lines, the second source lines, and the bitlines, each bitcell including first and second access transistors in the device level and having gate terminals coupled to one of the wordlines and source terminals coupled to respective ones of the first and second source lines, spin Hall metal in a lower portion of a second lowest metal interconnect layer of the semiconductor device and coupling drain terminals of the first and second access transistors, and a magnetic tunnel junction (MTJ) in an upper portion of the second lowest metal interconnect layer and having a bottom terminal coupled to the spin Hall metal and a top terminal coupled to one of the bitlines.

Example 27 includes the subject matter of Example 26, where each bitcell includes only two transistors and one MTJ.

Example 28 includes the subject matter of any of Examples 26-27, where for each bitcell, each of the first and second access transistors includes two gate electrodes for coupling two corresponding source regions to a single drain region.

Example 29 includes the subj ect matter of Example 28, where each wordline includes two corresponding wordlines, and for each bitcell, the two gate electrodes of each of the first and second access transistors are respectively coupled to the two corresponding wordlines of the one of the wordlines.

Example 30 includes the subject matter of any of Examples 28-29, where for each bitcell, each of the first and second access transistors further includes: two corresponding source contacts coupling the two corresponding source regions to a respective one of the first and second source lines; and a drain contact coupling the drain region to the drain terminal of a respective one of the first and second access transistors.

Example 31 includes the subject matter of Example 30, where each of the first and second access transistors of adj acent ones of the bitcells in the second direction share a common said source region and a common said corresponding source contact

Example 32 includes the subject matter of any of Examples 26-31, where each bitcell further includes first and second metal stubs in a lowest portion of the second lowest metal interconnect layer, the first and second metal stubs respectively coupling the drain terminals of the first and second access transistors to the spin Hall metal.

Example 33 includes the subject matter of Example 32, where for each bitcell, the MTJ is equidistant to the first and second metal stubs.

Example 34 includes the subject matter of any of Examples 26-33, where for each bitcell, the MTJ includes: a free magnet coupled to the spin Hall metal; a fixed magnet coupled to the one of the bitlines; and a tunnel barrier separating the free magnet and the fixed magnet.

Example 35 includes the subject matter of any of Examples 26-34, where for each bitcell, the MTJ overlaps one of the first and second source lines in a vertical direction perpendicular to the first and second directions.

Example 36 includes the subject matter of any of Examples 26-35, where the spin Hall metal includes one or more of beta tantalum (β-Ta), beta tungsten (β-W), and platinum (Pt).

Example 37 includes the subject matter of any of Examples 26-36, where the semiconductor device is a microprocessor and the bitcells are an embedded memory cell array of the microprocessor.

Example 38 is a method of manufacturing a spin Hall effect (SHE) magnetoresi stive random-access memory (MRAM) bitcell, the method including: forming first and second access transistors on a substrate in a device level of a semiconductor device; forming a wordline in the device level and coupled to gate terminals of the first and second access transistors; forming a first source line and a second source lines in a lowest metal interconnect layer of the semiconductor device and coupled to source terminals of the first and second access transistors, respectively; forming spin Hall metal in a lower portion of a second lowest metal interconnect layer of the semiconductor device, the spin Hall metal coupling drain terminals of the first and second access transistors; forming a magnetic tunnel junction (MTJ) in an upper portion of the second lowest metal interconnect layer, the MTJ having a bottom terminal coupled to the spin Hall metal; and forming a bitline in a third lowest metal interconnect layer of the semiconductor device and coupled to a top terminal of the MTJ.

Example 39 includes the subject matter of Example 38, further including forming only two transistors and one MTJ in the bitcell.

Example 40 includes the subject matter of any of Examples 38-39, where the forming of each of the first and second access transistors includes forming two gate electrodes for coupling two corresponding source regions to a single drain region

Example 41 includes the subject matter of Example 40, where the forming of the wordline includes forming two corresponding wordlines respectively coupled to the two gate electrodes of each of the first and second access transistors.

Example 42 includes the subject matter of any of Examples 40-41, where the forming of each of the first and second access transistors further includes: forming two corresponding source contacts coupling the two corresponding source regions to a respective one of the first and second source lines; and forming a drain contact coupling the drain region to the drain terminal of a respective one of the first and second access transistors.

Example 43 includes the subject matter of any of Examples 38-42, further including forming first and second metal stubs in a lowest portion of the second lowest metal interconnect layer, the first and second metal stubs respectively coupling the drain terminals of the first and second access transistors to the spin Hall metal.

Example 44 includes the subject matter of Example 43, where the forming of the MTJ includes forming the MTJ equidistant to the first and second metal stubs.

Example 45 includes the subject matter of any of Examples 38-44, where the forming of the MTJ includes: forming a free magnet coupled to the spin Hall metal; forming a tunnel barrier on the free magnet; and forming a fixed magnet on the tunnel barrier, the tunnel barrier separating the free magnet and the fixed magnet, where the forming of the bitline includes coupling the bitline to the fixed magnet.

Example 46 includes the subject matter of any of Examples 38-45, where the forming of the MTJ includes forming the MTJ to overlap one of the first and second source lines in a vertical direction.

Example 47 includes the subject matter of any of Examples 38, where the forming of the spin Hall metal includes forming the spin Hall metal from at least one or more of beta tantalum (β-Ta), beta tungsten (β-W), and platinum (Pt).

Example 48 includes the subject matter of any of Examples 38-47, further including: forming a microprocessor as the semiconductor device; and forming the bitcell as an embedded memory cell of the microprocessor.

Example 49 includes the subject matter of any of Examples 38-48, further including forming a write driver to write data of a first state to the bitcell by: driving the wordline for a first period to turn on the first and second access transistors while supplying voltage of a first polarity to the first source line and supplying voltage of a second polarity opposite the first polarity to the second source line; driving the wordline for a second period following the first period while supplying the second polarity voltage to the first source line and supplying the first polarity voltage to the second source line; and supplying a first voltage to the bitline for a third period overlapping and following the second period and while not driving the wordline during the following portion of the third period.

Example 50 includes the subject matter of Example 49, further including forming a customizing circuit to adjust a level of the first voltage and a length of the overlapping portion of the third period.

Example 51 includes the subject matter of any of Examples 49-50, further including forming a read driver to read data from the bitcell by driving the wordline while supplying the second polarity voltage to the first and second source lines and while supplying a second voltage to the bitline.

Example 52 includes the subject matter of any of Examples 38-51, further including: forming wordlines in the device level, extending in a first direction, and including the wordline; forming first source lines and second source lines in the lowest metal interconnect layer, extending in a second direction crossing the first direction, the first source lines including the first source line and the second source lines including the second source line; forming bitlines in the third lowest metal interconnect layer, extending in the second direction, and including the bitline; and forming bitcells where the wordlines cross the first source lines, the second source lines, and the bitlines, the bitcells including the bitcell, each of the bitcells being formed as in the bitcell with one of the wordlines being the wordline, one of the first source lines being the first source line, one of the second source lines being the second source line, and one of the bitlines being the bitline.

Example 53 includes the subject matter of Example 52, where for each of the bitcells, the forming of each of the first and second access transistors includes: forming two gate electrodes for coupling two corresponding source regions to a single drain region; and forming two corresponding source contacts coupling the two corresponding source regions to a respective one of the first and second source lines, and the forming of each of the first and second access transistors of adjacent ones of the bitcells in the second direction includes forming a shared said source region and a shared said corresponding source contact.

Example 54 includes the subject matter of any of Examples 52-53, further including: forming a microprocessor as the semiconductor device; and forming the bitcells as an embedded memory cell array of the microprocessor.

Example 55 is a method of writing data to a spin Hall effect (SHE) magnetoresi stive random-access memory (MRAM) including a SHE-MRAM bitcell array including wordlines extending in a first direction, first source lines and second source lines extending in a second direction crossing the first direction, bitlines extending in the second direction, and bitcells where the wordlines cross the first source lines, the second source lines, and the bitlines, each bitcell including first and second access transistors having gate terminals coupled to one of the wordlines and source terminals coupled to respective ones of the first and second source lines, spin Hall metal coupling drain terminals of the first and second access transistors, and a magnetic tunnel junction (MTJ) having a bottom terminal coupled to the spin Hall metal and a top terminal coupled to one of the bitlines, the method including: writing data of a first state to one of the bitcells by driving the one of the wordlines for a first period to turn on the first and second access transistors while supplying voltage of a first polarity to the first source line and supplying voltage of a second polarity opposite the first polarity to the second source line, driving the one of the wordlines for a second period following the first period while supplying the second

polarity voltage to the first source line and supplying the first polarity voltage to the second source line, and supplying a first voltage to the one of the bitlines for a third period overlapping and following the second period and while not driving the one of the wordlines during the following portion of the third period.

Example 56 includes the subject matter of Example 55, where the SHE-MRAM further includes a customizing circuit, the method further including adjusting a level of the first voltage and a length of the overlapping portion of the third period using the customizing circuit.

Example 57 includes the subject matter of Example 56, further including adjusting lengths of the first and second periods using the customizing circuit.

Example 58 includes the subject matter of any of Examples 56-57, further including adjusting a length of the following portion of the third period using the customizing circuit.

Example 59 includes the subject matter of any of Examples 55-58, further including writing data of a second state opposite the first state to the one of the bitcells by: driving the one of the wordlines for the first period while supplying the second polarity voltage to the first source line and supplying the first polarity voltage to the second source line; driving the one of the wordlines for the second period while supplying the first polarity voltage to the first source line and supplying the second polarity voltage to the second source line; and supplying the first voltage to the one of the bitlines for the third period while not driving the one of the wordlines during the following portion of the third period.

Example 60 includes the subject matter of any of Examples 55-59, further including reading data from the one of the bitcells by driving the one of the wordlines while supplying the second polarity voltage to the first and second source lines and while supplying a second voltage to the one of the bitlines.

Example 61 includes the subject matter of Example 60, where SHE-MRAM further includes a customizing circuit, the method further including adjusting a level of the second voltage using the customizing circuit.

Example 62 includes the subject matter of Example 61, where the adjusting of the level of the second voltage includes adjusting the second voltage to a different voltage than the first voltage.

Example 63 is a method of manufacturing a spin Hall effect (SHE) magnetoresi stive random-access memory (MRAM) bitcell array including bitcells where wordlines cross first source lines, second source lines, and bitlines, the method including: forming the wordlines on a substrate in a device level of a semiconductor device, the wordlines extending in a first direction; for each bitcell, forming first and second access transistors in the device level, the first and second access transistors having gate terminals coupled to one of the wordlines; forming the first source lines and the second source lines in a lowest metal interconnect layer of the semiconductor device, the first and second source lines extending in a second direction crossing the first direction, each first access transistor being coupled to one of the first source lines and each second access transistor being coupled to one of the second source lines; for each bitcell, forming spin Hall metal in a lower portion of a second lowest metal interconnect layer of the semiconductor device, the spin Hall metal coupling drain terminals of the first and second access transistors; for each bitcell, forming a magnetic tunnel junction (MTJ) in an upper portion of the second lowest metal interconnect layer, the MTJ having a bottom terminal coupled to the spin Hall metal; and forming the bitlines in a third lowest metal interconnect layer of the semiconductor device, the bitlines extending in the second direction, each MTJ having a top terminal coupled to one of the bitlines.

Example 64 includes the subject matter of Example 63, further including, for each bitcell, forming only two transistors and one MTJ.

Example 65 includes the subject matter of any of Examples 63-64, where for each bitcell, the forming of each of the first and second access transistors includes forming two gate electrodes for coupling two corresponding source regions to a single drain region.

Example 66 includes the subject matter of Example 65, where the forming of each wordline includes forming two corresponding wordlines, and for each bitcell, the forming of each of the first and second access transistors further includes respectively coupling the two gate electrodes to the two corresponding wordlines of the one of the wordlines.

Example 67 includes the subject matter of any of Examples 65-66, where for each bitcell, the forming of each of the first and second access transistors further includes: forming two corresponding source contacts coupling the two corresponding source regions to a respective one of the first and second source lines; and forming a drain contact coupling the drain region to the drain terminal of a respective one of the first and second access transistors.

Example 68 includes the subject matter of Example 67, where the forming of each of the first and second access transistors of adjacent ones of the bitcells in the second direction includes forming a shared said source region and a shared said corresponding source contact.

Example 69 includes the subject matter of any of Examples 63-68, further including, for each bitcell, forming first and second metal stubs in a lowest portion of the second lowest metal interconnect layer, the first and second metal stubs respectively coupling the drain terminals of the first and second access transistors to the spin Hall metal.

Example 70 includes the subject matter of Example 69, where for each bitcell, the forming of the MTJ includes forming the MTJ equidistant to the first and second metal stubs.

Example 71 includes the subject matter of any of Examples 63-70, where for each bitcell, the forming of the MTJ includes: forming a free magnet coupled to the spin Hall metal; forming a tunnel barrier on the free magnet; and forming a fixed magnet on the tunnel barrier, the tunnel barrier separating the free magnet and the fixed magnet, where the forming of the one of the bitlines includes coupling the one of the bitlines to the fixed magnet.

Example 72 includes the subject matter of any of Examples 63-71, where for each bitcell, the forming of the MTJ includes forming the MTJ to overlap one of the first and second source lines in a vertical direction perpendicular to the first and second directions.

Example 73 includes the subject matter of any of Examples 63-72, where the forming of the spin Hall metal includes forming the spin Hall metal from at least one or more of beta tantalum (β-Ta), beta tungsten (β-W), and platinum (Pt).

Example 74 includes the subject matter of any of Examples 63-73, further including: forming a microprocessor as the semiconductor device; and forming the bitcells as an embedded memory cell array of the microprocessor.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.