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1. (WO2018102001) EQUALIZING ERASE DEPTH IN DIFFERENT BLOCKS OF MEMORY CELLS
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CLAIMS

We claim:

1. An apparatus, comprising:

a plurality of blocks (BLK0-3) of memory cells (702-716, 722-736, 742-756, 762-776), the memory cells are arranged in strings (NS1, NS2, 700n, 71 On, 720n and 73 On), each string comprising a source end (613), a drain end (615), a channel (700a, 710a, 720a, 730a) extending between the source end and the drain end, and a select gate transistor (700, 701, 720, 721, 740, 741, 760, 761) at the source end;

a voltage source (2120) which comprises a pass gate (2124) and which provides a select gate voltage;

a voltage source (SLVS, 2130) which provides a source end voltage; and

a control circuit (110, 122), the control circuit configured to, in an erase operation for a selected block among the plurality of blocks, connect the select gate voltage to the select gate transistors and connect the source end voltage to the source ends to charge up the channel of each string of the selected block, wherein each select gate transistor has a positive channel-to-control gate voltage and a magnitude of the source end voltage minus the select gate voltage is based on an increasing function of a distance (dO, dl and d2) of the selected block from the pass gate.

2. The apparatus of claim 1, wherein:

the channel of each string of the selected block is charged up by gate-induced drain leakage.

3. The apparatus of claim 1 or 2, wherein:

the control circuit is configured to increase the source end voltage by a step size in erase loops; and

an initial magnitude of the source end voltage in the erase loops is based on an increasing function of the distance.

4. The apparatus of any one of claims 1 to 3, wherein:

the control circuit is configured to increase the source end voltage by a step size in erase loops; and

the step size is an increasing function of the distance.

5. The apparatus of any one of claims 1 to 4, wherein:

the control circuit is configured to set a duration (wl, w2) of the source end voltage based on an increasing function of the distance in response to a determination that a temperature is below a threshold.

6. The apparatus of any one of claims 1 to 5, wherein:

the memory cells are connected to word lines (WLD4-WLD2); and

the control circuit, in the erase operation, is configured to apply a voltage to the word lines which is based on a decreasing function of the distance.

7. The apparatus of any one of claims 1 to 6, wherein:

the control circuit, to perform the erase operation, is configured to connect the select gate voltage to the select gate transistors and connect the source end voltage to the source ends in a series of erase loops, and to perform a verify test in each erase loop, wherein after the verify test is passed, the control circuit is configured to provide an additional erase pulse (1404) to the selected block if the distance exceeds a threshold.

8. The apparatus of any one of claims 1 to 7, wherein:

the magnitude is lowest for a block which is closest to the pass gate and highest for a block which is further from the pass gate.

9. The apparatus of any one of claims 1 to 8, wherein:

the memory cells are connected to word lines (WLD4-WLD2); and

the control circuit, in the erase operation, is configured to set a control gate voltage for the memory cells which is less than the select gate when the channel of each string is charged up.

10. The apparatus of any one of claims 1 to 9, wherein:

the control circuit is configured to set a magnitude of the source end voltage based on an increasing function of the distance in response to a determination that a temperature is above a threshold.

11. The apparatus of any one of claims 1 to 10, wherein:

the source end of each string of the selected block comprises a source diffusion region (2133) which is common to the plurality of blocks; and

the control circuit is configured to provide a common magnitude and duration of the source end voltage during erase operations for each of the plurality of blocks.

12. A method, comprising:

in connection with an erase operation of a selected block (BLK0-3) of memory cells (702-716, 722-736, 742-756, 762-776), wherein the memory cells are arranged in strings (NSl, NS2, 700n, 71 On, 720n and 73 On), each string comprising a source end (613), a drain end (615), a channel (700a, 710a, 720a, 730a) extending between the source end and the drain end, and a select gate transistor (700, 701, 720, 721, 740, 741, 760, 761):

providing a pass gate (2124) of a voltage source (2120) in a conductive state to pass a select gate voltage from the voltage source to each select gate transistor while providing a source end voltage to the source end of each string, wherein the select gate voltage is based on a function of a distance (dO, dl and d2) between the pass gate and the selected block.

13. The method of claim 12, wherein:

a magnitude of the select gate voltage (Vsgs) is based on a decreasing function of the distance.

14. The method of claim 12 or 13, wherein:

a duration of the select gate voltage is based on an increasing function of the distance.

15. The method of any one of claims 12 to 14, wherein:

the selected block is among a plurality of blocks, each block of the plurality of blocks is at a different distance from the pass gate, the blocks are in subsets and a different select gate voltage is cross-referenced to each subset.