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Einstellungen

Einstellungen

1. WO2008141898 - VERFAHREN ZUR HERSTELLUNG EINER ELEKTRONISCHEN BAUGRUPPE

Veröffentlichungsnummer WO/2008/141898
Veröffentlichungsdatum 27.11.2008
Internationales Aktenzeichen PCT/EP2008/055175
Internationales Anmeldedatum 28.04.2008
IPC
H05K 1/18 2006.01
HElektrotechnik
05Elektrotechnik, soweit nicht anderweitig vorgesehen
KGedruckte Schaltungen; Gehäuse oder konstruktive Einzelheiten von elektrischen Geräten; Herstellung von Baugruppen aus elektrischen Elementen
1Gedruckte Schaltungen
18Gedruckte Schaltungen, die baulich mit nichtgedruckten elektrischen Schaltelementen vereinigt sind
CPC
H01L 2224/04105
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
H01L 2224/24227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
18High density interconnect [HDI] connectors; Manufacturing methods related thereto
23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
24of an individual high density interconnect connector
241Disposition
24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
24221the body and the item being stacked
24225the item being non-metallic, e.g. insulating substrate with or without metallisation
24227the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
H01L 2224/32145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32135the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
32145the bodies being stacked
H01L 2224/32245
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32245the item being metallic
H01L 2224/73267
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73251on different surfaces
73267Layer and HDI connectors
H01L 2224/82039
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
82by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
82009Pre-treatment of the connector or the bonding area
8203Reshaping, e.g. forming vias
82035by heating means
82039using a laser
Anmelder
  • ROBERT BOSCH GMBH [DE/DE]; Postfach 30 02 20 70442 Stuttgart, DE (AllExceptUS)
  • WÜRTH ELEKTRONIK ROT AM SEE GMBH & CO. KG [DE/DE]; Rudolf-Diesel-Str. 10 74585 Rot Am See, DE (AllExceptUS)
  • FRAUNHOFER GESELLSCHAFT [DE/DE]; Hansastr. 27c 80686 München, DE (AllExceptUS)
  • SCHAAF, Ulrich [DE/DE]; DE (UsOnly)
  • KUGLER, Andreas [DE/DE]; DE (UsOnly)
  • BECKER, Karl-Friederich [DE/DE]; DE (UsOnly)
  • NEUMANN, Alexander [DE/DE]; DE (UsOnly)
  • KOSTELNIK, Jan [DE/DE]; DE (UsOnly)
Erfinder
  • SCHAAF, Ulrich; DE
  • KUGLER, Andreas; DE
  • BECKER, Karl-Friederich; DE
  • NEUMANN, Alexander; DE
  • KOSTELNIK, Jan; DE
Gemeinsamer Vertreter
  • ROBERT BOSCH GMBH; Postfach 30 02 20 70442 Stuttgart, DE
Prioritätsdaten
10 2007 024 189.724.05.2007DE
Veröffentlichungssprache Deutsch (DE)
Anmeldesprache Deutsch (DE)
Designierte Staaten
Titel
(DE) VERFAHREN ZUR HERSTELLUNG EINER ELEKTRONISCHEN BAUGRUPPE
(EN) METHOD FOR PRODUCING AN ELECTRONIC ASSEMBLY
(FR) PROCÉDÉ DE PRODUCTION D'UN COMPOSANT ÉLECTRONIQUE
Zusammenfassung
(DE)
Die Erfindung betrifft ein Verfahren zur Herstellung einer elektronischen Baugruppe (21), wobei in einem ersten Schritt mindestens ein elektronisches Bauelement (9) auf einer isolierenden Schicht (5) einer leitfähigen Folie (1) befestigt wird, die leitfähige Folie (1) mit dem elektronischen Bauelement (9) auf einen Leiterplattenträger (13) auflaminiert wird und anschließend eine Leiterbahnstruktur (15) durch Strukturieren der leitfähigen Folie (1) ausgebildet wird. Dabei liegt der Ausdehnungskoeffizient der isolierenden Schicht (5) zwischen dem Ausdehnungskoeffizienten des Leiterplattenträgers (13) und dem Ausdehnungskoeffizienten der Leiterbahnstruktur (15), und/oder elektronische Bauteile (9), die für eine Ankontaktierung mit der Leiterbahnstruktur (15) kleine Durchgänge benötigen, werden weiter in die isolierende Schicht (5) eingedrückt als elektronische Bauteile (9), die größere Durchgänge in der isolierenden Schicht (5) benötigen, und/oder vor dem Aufbringen einer weiteren Leiterbahnstruktur (27) wird die Leiterbahnstruktur (15) aufgespreizt.
(EN)
The invention relates to a method for producing an electronic assembly (21), wherein, in a first step, at least one electronic component (9) is fastened on an isolating layer (5) of a conductive film (1), the conductive film (1) with the electronic component (9) is laminated onto a printed circuit board carrier (13) and finally a conductor structure (15) is formed by structuring the conductive film (1). The coefficient of expansion of the isolating layer (5) is between the coefficient of expansion of the printed circuit board carrier (13) and the coefficient of expansion of the conductor structure (15), and/or electronic components (9), which need small passages for contacting with the conductor structure (15), are pressed further into the isolating layer (5) than electronic components (9), which need larger passages in the isolating layer (5), and/or the conductor structure (15) is forced apart before the application of a further conductor structure (27).
(FR)
L'invention concerne un procédé de production d'un composant électronique (21). Dans une première étape, au moins un composant électronique (9) est fixé sur une couche isolante (5) d'un film conducteur (1), le film conducteur (1) et le composant électronique (9) sont laminés sur un support (13) de carte imprimée puis une structure (15) de pistes conductrices est réalisée par structuration du film conducteur (1). Le coefficient de dilatation de la couche isolante (5) se situe alors entre le coefficient de dilatation du support (13) de carte imprimée et le coefficient de dilatation de la structure (15) de pistes conductrices et/ou les composants électroniques (9) nécessitant de petits passages dans la couche isolante pour la liaison conductrice avec la structure (15) de pistes conductrices, sont enfoncés plus profond dans la couche isolante (5) que les composants électroniques (9) nécessitant des passages plus grands dans la couche isolante (5), et/ou la structure (15) de pistes conductrices est écartée avant le montage d'une autre structure (27) de pistes conductrices.
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