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Einstellungen

Einstellungen

1. WO2000035014 - VERFAHREN ZUR HERSTELLUNG EINES INTEGRIERTEN SCHALTKREISES

Veröffentlichungsnummer WO/2000/035014
Veröffentlichungsdatum 15.06.2000
Internationales Aktenzeichen PCT/DE1999/003928
Internationales Anmeldedatum 08.12.1999
Antrag nach Kapitel 2 eingegangen 05.06.2000
IPC
H01L 23/495 2006.01
HElektrotechnik
01Grundlegende elektrische Bauteile
LHalbleiterbauelemente; elektrische Festkörperbauelemente, soweit nicht anderweitig vorgesehen
23Einzelheiten von Halbleiter- oder anderen Festkörperbauelementen
48Anordnungen zur Stromleitung zu oder von dem im Betrieb befindlichen Festkörper, z.B. Zuleitungen oder Anschlüsse
488bestehend aus gelöteten oder gebondeten Anordnungen
495Leiterrahmen
CPC
H01L 2224/05599
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/85399
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
85using a wire connector
8538Bonding interfaces outside the semiconductor or solid-state body
85399Material
H01L 23/4951
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
488consisting of soldered ; or bonded; constructions
495Lead-frames ; or other flat leads
49503characterised by the die pad
4951Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
H01L 24/48
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
H01L 2924/00014
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
00014the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Anmelder
  • INFINEON TECHNOLOGIES AG [DE/DE]; Saint-Martin-Strasse 53 D-81541 München, DE (AllExceptUS)
  • FERSTL, Klemens [DE/DE]; DE (UsOnly)
  • JANCZEK, Thies [DE/DE]; DE (UsOnly)
  • NEU, Achim [DE/DE]; DE (UsOnly)
Erfinder
  • FERSTL, Klemens; DE
  • JANCZEK, Thies; DE
  • NEU, Achim; DE
Vertreter
  • SCHWEIGER, Martin ; Leopoldstrasse 77 80802 München, DE
Prioritätsdaten
198 56 833.909.12.1998DE
Veröffentlichungssprache Deutsch (DE)
Anmeldesprache Deutsch (DE)
Designierte Staaten
Titel
(DE) VERFAHREN ZUR HERSTELLUNG EINES INTEGRIERTEN SCHALTKREISES
(EN) METHOD FOR PRODUCING AN INTEGRATED SWITCHING CIRCUIT
(FR) PROCEDE DE PRODUCTION D'UN CIRCUIT INTEGRE
Zusammenfassung
(DE)
Bei einem Verfahren zur Herstellung eines integrierten Schaltkreises wird ein Halbleiterwafer mit Substratbereichen (12), auf denen integrierte Schaltungen mit Anschlußkontakten (13) ausgebildet sind, mit Leadframes mit Leiterbahnen (16) bestückt. Dazu wird zunächst Kleber (14) auf dem Halbleiterwafer (12) im Bereich der Anschlußkontakte (13) aufgebracht, und zwar mit einem Druckverfahren wie Schablonendruck oder Offsetdruck. Anschließend werden die Leadframes auf die Substratbereiche (12) aufgebracht.
(EN)
The invention relates to a method for producing an integrated switching circuit in which a semiconductor wafer is fitted with substrate regions (12), on which integrated circuits comprising terminal contacts (13) are configured. The semiconductor wafer is also fitted with lead frames having conducting paths (16). To this end, an adhesive (14) is firstly deposited on the semiconductor wafer (12) in the vicinity of the terminal contacts (13) while using a printing method such as stencil printing or offset printing. The lead frames are subsequently deposited on the substrate regions (12).
(FR)
L'invention concerne un procédé de production d'un circuit intégré, selon lequel une tranche de semi-conducteur, comportant des zones de substrat (12) sur lesquelles sont formés des circuits intégrés présentant des contacts de raccordement (13), est équipée d'un réseau de conducteurs présentant des pistes conductrices (16). A cet effet, de la colle (14) est d'abord appliquée sur la tranche de semi-conducteur (12), dans la zone des contacts de raccordement (13), cela selon un procédé d'impression tel que la sérigraphie ou l'impression offset. Ensuite, les réseaux de conducteurs sont appliqués sur les zones de substrat (12).
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