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1. WO1998000867 - INTEGRIERTE HALBLEITERSCHALTUNG

Veröffentlichungsnummer WO/1998/000867
Veröffentlichungsdatum 08.01.1998
Internationales Aktenzeichen PCT/DE1997/001273
Internationales Anmeldedatum 19.06.1997
Antrag nach Kapitel 2 eingegangen 31.10.1997
IPC
H01L 23/495 2006.1
HSektion H Elektrotechnik
01Grundlegende elektrische Bauteile
LHalbleiterbauelemente; elektrische Festkörperbauelemente, soweit nicht anderweitig vorgesehen
23Einzelheiten von Halbleiterbauelementen oder anderen Festkörperbauelementen
48Anordnungen zur Stromleitung zu oder von dem im Betrieb befindlichen Festkörper, z.B. Zuleitungen oder Anschlüsse
488bestehend aus gelöteten oder gebondeten Anordnungen
495Leiterrahmen
CPC
H01L 2224/45144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
45099Material
451with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
45138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
45144Gold (Au) as principal constituent
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48247
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48245the item being metallic
48247connecting the wire to a bond pad of the item
H01L 2224/4826
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48245the item being metallic
4826Connecting between the body and an opposite side of the item with respect to the body
H01L 2224/73215
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73201on the same surface
73215Layer and wire connectors
H01L 23/28
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
Anmelder
  • SIEMENS AKTIENGESELLSCHAFT [DE]/[DE] (AllExceptUS)
  • POHL, Jens [DE]/[DE] (UsOnly)
  • GOLZ, Bruno [DE]/[DE] (UsOnly)
  • WIDNER, Harald [DE]/[DE] (UsOnly)
Erfinder
  • POHL, Jens
  • GOLZ, Bruno
  • WIDNER, Harald
Prioritätsdaten
196 26 087.628.06.1996DE
Veröffentlichungssprache Deutsch (de)
Anmeldesprache Deutsch (DE)
Designierte Staaten
Titel
(DE) INTEGRIERTE HALBLEITERSCHALTUNG
(EN) INTEGRATED SEMICONDUCTOR CIRCUIT
(FR) CIRCUIT INTEGRE A SEMI-CONDUCTEUR
Zusammenfassung
(DE) Die Erfindung bezieht sich auf eine integrierte Halbleiterschaltung mit einem Halbleiterchip (1), einem den Halbleiterchip aufnehmenden Gehäuse (5) und einem Leiterrahmen (4) zur elektrischen Verbindung zwischen Kontaktflächen (2) des Halbleiterchips (1) und äußeren Anschlüssen (7) der integrierten Halbleiterschaltung. Die Leiter des Leiterrahmens sind dabei in den Bereichen des Gehäuses (5), in denen der Abstand zwischen dem Rand des Gehäuses (5) und dem Halbleiterchip (1) relativ groß ist, zur Mittelebene (9) des Gehäuses (5) abgesenkt, so daß in diesen Bereichen die Leiter (3) des Leiterrahmens (4) Absenkungen (8) aufweisen.
(EN) The invention relates to an integrated semiconductor circuit having a semiconductor chip (1), a housing (5) holding the semiconductor chip, and a lead frame (4) for electrical connection between contact surfaces (2) of the semiconductor chip (1) and external terminals (7) of the integrated semiconductor circuit. The leads of the lead frame are lowered, in the areas of the housing (5) in which the distance between the edge of the housing (5) and the semiconductor chip (1) is relatively large, to the central plane (9) of the housing (5) with the result that the leads (3) of the lead frame (4) in said areas have lowered sections (8).
(FR) L'invention concerne un circuit intégré à semi-conducteur, comportant une puce à semi-conducteur (1), un boîtier (5) destiné à contenir ladite puce à semi-conducteur et une baie conductrice (4) pour assurer la liaison électrique entre les surfaces de contact (2) de la puce à semi-conducteur (1) et les connexions (7) extérieures du circuit intégré à semi-conducteur. A cet effet, les conducteurs de la baie conductrice sont abaissés au plan médian (9) du boîtier (5), dans les zones du boîtier (5) où l'écart entre le bord dudit boîtier (5) et la puce à semi-conducteur (1) est relativement important, de manière que dans cette zone, les conducteurs de la baie conductrice (4) présentent des sections abaissées (8).
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