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1. US20120104605 - Chip design having integrated fuse and method for the production thereof

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Amt
Vereinigte Staaten von Amerika
Aktenzeichen/Anmeldenummer 13141687
Anmeldedatum 23.11.2009
Veröffentlichungsnummer 20120104605
Veröffentlichungsdatum 03.05.2012
Erteilungsnummer 08525331
Erteilungsdatum 03.09.2013
Veröffentlichungsart B2
IPC
H01L 23/48
HSektion H Elektrotechnik
01Grundlegende elektrische Bauteile
LHalbleiterbauelemente; elektrische Festkörperbauelemente, soweit nicht anderweitig vorgesehen
23Einzelheiten von Halbleiterbauelementen oder anderen Festkörperbauelementen
48Anordnungen zur Stromleitung zu oder von dem im Betrieb befindlichen Festkörper, z.B. Zuleitungen oder Anschlüsse
CPC
H01L 23/3114
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
3107the device being completely enclosed
3114the device being a chip scale package, e.g. CSP
H01L 23/5256
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
525with adaptable interconnections
5256comprising fuses, i.e. connections having their state changed from conductive to non-conductive
H01L 24/49
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
49of a plurality of wire connectors
H01L 2224/05554
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0555Shape
05552in top view
05554being square
H01L 2224/49113
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
49of a plurality of wire connectors
491Disposition
4911the connectors being bonded to at least one common bonding area, e.g. daisy chain
49113the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
H01L 2924/00014
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
00014the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Anmelder Ilzer Karl
AMS AG
Minixhofer Rainer
Manninger Mario
Erfinder Ilzer Karl
Minixhofer Rainer
Manninger Mario
Vertreter McDermott Will & Emery LLP
Prioritätsdaten 102008064428 22.12.2008 DE
Titel
(EN) Chip design having integrated fuse and method for the production thereof
front page image
Zusammenfassung
(EN)

A chip design (1) comprising an external supply connection (VBAT), an internal supply connection (VDD), an integrated circuit (2) that is coupled to the internal supply connection (VDD) for voltage supply, and a fuse (3) that electrically connects the internal supply connection (VBAT) and is arranged within the chip design (1).
Verwandte Patentdokumente
DE102008064428
JP2012513078
WO/2010/072492
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