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1. (WO2019066880) GROUP III-V SEMICONDUCTOR DEVICES HAVING ASYMMETRIC SOURCE AND DRAIN STRUCTURES
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CLAIMS

What is claimed is:

1. An integrated circuit structure, comprising:

a gallium arsenide layer on a substrate;

a channel structure on the gallium arsenide layer, the channel structure comprising indium, gallium and arsenic;

a source structure at a first end of the channel structure and a drain structure at a second end of the channel structure, the drain structure having a wider band gap than the source structure; and

a gate structure over the channel structure.

2. The integrated circuit structure of claim 1, wherein the source structure has approximately the same band gap as the channel structure.

3. The integrated circuit structure of claim 1, wherein the source structure and the drain structure are doped with N-type dopants.

4. The integrated circuit structure of claim 3, wherein the concentration of N-type dopants in the drain structure is less than the concentration of N-type dopants in the source structure.

5. The integrated circuit structure of claim 1, further comprising:

an intrinsic region between the drain structure and the channel structure, the intrinsic region comprising a same semiconductor material as the drain structure.

6. The integrated circuit structure of claim 1, further comprising:

a dielectric layer between the channel structure and the gate structure.

7. The integrated circuit structure of claim 1, further comprising:

a first conductive contact on the drain structure, and a second conductive contact on the source structure.

8. The integrated circuit structure of claim 1, wherein the channel structure is a fin structure.

9. The integrated circuit structure of claim 1, wherein the channel structure is a nanowire structure.

10. The integrated circuit structure of claim 1, wherein the drain structure comprises indium phosphide (InP), and the source structure comprises indium gallium arsenide (InGaAs) or indium arsenide (InAs).

11. A method of fabricating an integrated circuit structure, the method comprising:

forming a first semiconductor layer on a gallium arsenide layer above a substrate;

forming a gate structure over the first semiconductor layer;

masking a second side of the gate structure but not a first side of the gate structure with a mask;

removing a portion of the first semiconductor layer at the first side of the gate structure; removing the mask;

forming a second semiconductor layer at the first side of the gate structure, the second semiconductor layer having a wider band gap than the first semiconductor layer; and

implanting N-type dopants to form a drain structure in the second semiconductor layer at the first side of the gate structure and to form a source structure in the first semiconductor layer at the second side of the gate structure.

12. The method of claim 11, wherein the first semiconductor layer comprises indium, gallium and arsenic.

13. The method of claim 12, wherein the second semiconductor layer comprises indium and phosphorus.

14. The method of claim 11, wherein the concentration of N-type dopants in the drain structure is less than the concentration of N-type dopants in the source structure.

15. The integrated circuit structure of claim 11, further comprising:

forming a first conductive contact on the drain structure, and a second conductive contact on the source structure.

16. A method of fabricating an integrated circuit structure, the method comprising:

forming a first semiconductor layer on a gallium arsenide layer above a substrate;

forming a gate structure over the first semiconductor layer;

masking a first side of the gate structure but not a second side of the gate structure with a mask;

removing a portion of the first semiconductor layer at the second side of the gate structure;

removing the mask;

forming a second semiconductor layer at the second side of the gate structure, the first semiconductor layer having a wider band gap than the second semiconductor layer; and

implanting N-type dopants to form a drain structure in the first semiconductor layer at the first side of the gate structure and to form a source structure in the second semiconductor layer at the second side of the gate structure.

17. The method of claim 16, wherein the second semiconductor layer comprises indium, gallium and arsenic.

18. The method of claim 17, wherein the first semiconductor layer comprises indium and phosphorus.

19. The method of claim 16, wherein the concentration of N-type dopants in the drain structure is less than the concentration of N-type dopants in the source structure.

20. The integrated circuit structure of claim 16, further comprising:

forming a first conductive contact on the drain structure, and a second conductive contact on the source structure.