بعض محتويات هذا التطبيق غير متوفرة في الوقت الحالي.
إذا استمرت هذه الحالة ، يرجى الاتصال بنا علىتعليق وإتصال
1. (WO2019046050) MEMORY ARRAY RESET READ OPERATION
ملاحظة: نص مبني على عمليات التَعرف الضوئي على الحروف. الرجاء إستخدام صيغ PDF لقيمتها القانونية

CLAIMS

What is claimed is:

1. A method, comprising:

identifying a part of a read command for setting at least one portion of a memory array to a temporary state;

identifying the at least one portion of the memory array based at least in part on the part of the read command; and

executing the part of the read command on the at least one portion of the memory array based at least in part on identifying the at least one portion of the memory array.

2. The method of claim 1, wherein executing the part of the read command comprises:

performing a read recovery part of a read operation, wherein the read operation comprises the read recovery part and a data sense part.

3. The method of claim 1, further comprising:

increasing a voltage applied to all word lines associated with the at least one portion to a first voltage above a threshold voltage of memory cells of the at least one portion;

increasing a voltage applied to at least one gate of at least one select gate device of the at least one portion to a second voltage above a second threshold voltage of the at least one select gate device; and

setting a voltage applied to a source, a drain, a bit line, or a combination thereof, of the at least one portion to a third voltage.

4. The method of claim 3, further comprising:

decreasing the voltage applied to all word lines from the first voltage to a fourth voltage based at least in part on achieving the first voltage; and

decreasing the voltage applied to the at least one gate of the at least one select gate device from the second voltage to below the second threshold voltage based at least in part on decreasing the voltage applied to all word lines.

5. The method of claim 1, wherein the temporary state comprises:

a transient state of memory cells of the at least one portion that includes retaining a word line to a channel potential difference of the memory cells at a level that is lower than a voltage of a source, a drain, a bit line, or a combination thereof of the memory cells after executing the part of the read command.

6. The method of claim 1, further comprising:

determining a duration since a last read operation for the at least one portion, wherein identifying the at least one portion of the memory array is based at least in part on determining the duration.

7. The method of claim 1, wherein the at least one portion corresponds to a single block of the memory array.

8. The method of claim 1, further comprising:

determining a mode of executing the part of the read command, wherein executing the part of the read command is based at least in part on determining the mode.

9. The method of claim 8, further comprising:

identifying a product design identification of the memory array, wherein determining the mode comprises determining a number of portions of the memory array on which the part of the read command is to be executed based at least in part on the product design identification.

10. The method of claim 9, further comprising:

executing the part of the read command concurrently on a plurality of portions of the memory array based at least in part on determining the number of portions.

11. The method of claim 10, wherein the plurality of portions comprises a total number of blocks of the memory array.

12. The method of claim 1, wherein the memory array comprises:

at least one three-dimensional Not- AND (NAND) memory cell.

13. The method of claim 1, further comprising:

receiving a request to perform the read command; and

initiating the part of the read command based at least in part on receiving the request.

14. The method of claim 13, further comprising:

identifying a set feature and a trim condition associated with the part of the read command; and

determining a configuration for executing the part of the read command based at least in part on identifying the set feature and the trim condition, wherein executing the part of the read command is based at least in part on determining the configuration.

15. The method of claim 14, wherein the set feature and the trim condition comprise an execution of the part of the read command on a single block.

16. The method of claim 14, wherein the set feature and the trim condition comprises an execution of the part of the read command on a maximum number of blocks defined by the trim condition.

17. The method of claim 14, wherein the set feature and the trim condition comprise an automatic execution of the part of the read command.

18. A method, comprising:

initiating a reset read command that sets at least one portion of a memory array into a temporary state;

applying, to all word lines associated with the at least one portion, a voltage that increases to a first voltage above a threshold voltage of memory cells of the at least one portion based at least in part on the initiating;

applying, to at least one gate of at least one select gate device of the at least one portion, a voltage that increases to a second voltage above a second threshold voltage of the at least one select gate device based at least in part on the initiating; and

setting a node of the at least one portion to a third voltage based at least in part on the initiating.

19. The method of claim 18, wherein the reset read command that sets the at least one portion of the memory array into the temporary state comprises:

initiating a transition of the at least one portion into the temporary state.

20. The method of claim 18, wherein the reset read command that sets the at least one portion of the memory array into the temporary state comprises:

maintaining the at least one portion in the temporary state.

21. The method of claim 18, wherein the node comprises a source, a drain, a bit line, or a combination thereof.

22. The method of claim 18, further comprising:

decreasing the voltage applied to all word lines associated with the at least one portion from the first voltage to a fourth voltage based at least in part on achieving the first voltage; and

decreasing the voltage applied to the at least one gate of the at least one select gate device of the at least one portion from the second voltage to below the second threshold voltage based at least in part on decreasing the voltage applied to all word lines.

23. The method of claim 22, wherein:

the first voltage is higher than the second voltage;

the second voltage is higher than the third voltage; and

the third voltage is a ground potential.

24. The method of claim 18,

wherein the reset read command comprises a read recovery part of a read operation,

wherein the read operation comprises the read recovery part and a data sense and transfer part, and

wherein the read recovery part comprises applying the voltage that increases to the first voltage above the threshold voltage of the memory cells, applying the voltage that increases to the second voltage above the second threshold voltage of the at least one select gate device, and setting the node of the at least one portion to the third voltage.

25. An apparatus, comprising:

a memory array;

a processor;

a controller coupled with the memory array and the processor, the controller being operable to:

identify a part of a read command for setting at least one portion of the memory array into a temporary state;

identify the at least one portion of the memory array based at least in part on the part of the read command; and

execute the part of the read command on the at least one portion of the memory array based at least in part on identifying the at least one portion of the memory array.

26. The apparatus of claim 25, wherein the controller is further operable to:

determine a number of portions on which the part of the read command is to be executed concurrently based at least in part on a product design identification of the memory array, wherein executing the part of the read command is based at least in part on determining the number of portions.

27. The apparatus of claim 25, wherein the controller is further operable to:

receive a request from the processor to execute the part of the read command, wherein identifying the part of the read command is based at least in part on the received request.

28. An apparatus, comprising:

a memory array;

a processor;

a controller coupled with the memory array and the processor, the controller being operable to:

initiate a reset read command that sets at least one portion of the memory array into a temporary state;

increase a voltage applied to all word lines associated with the at least one portion to a first voltage above a threshold voltage of memory cells of the at least one portion based at least in part on the initiating;

increase a voltage applied to at least one gate of at least one select gate device of the at least one portion to a second voltage above a second threshold voltage of the at least one select gate device based at least in part on the initiating; and

set a node of the at least one portion to a third voltage based at least in part on the initiating.

29. The apparatus of claim 28, wherein the reset read command that sets the at least one portion of the memory array into the temporary state comprises:

initiating a transition of the at least one portion into the temporary state or maintaining the at least one portion in the temporary state.

30. The apparatus of claim 28, wherein the controller is further operable to:

decrease the voltage applied to all word lines associated with the at least one portion from the first voltage to a fourth voltage based at least in part on achieving the first voltage;

decrease the voltage applied to the at least one gate of the at least one select gate device of the at least one portion from the second voltage to below the second threshold voltage based at least in part on decreasing the voltage applied to all word lines; and

wherein the node comprises a source, a drain, a bit line, or a combination thereof.

31. The apparatus of claim 28, wherein the controller is further operable to:

identify a set feature and a trim condition associated with the reset read command, wherein the set feature and the trim condition are set by the processor; and

determine a configuration for performing the reset read command based at least in part on identifying the set feature and the trim condition.

32. A method, comprising:

receiving a request to perform a part of a read command on a memory array; identifying a plurality of portions of the memory array based at least in part on the received request; and

executing a truncated read operation concurrently on the plurality of portions to set the plurality of portions in a first state based at least in part on identifying the plurality of portions.

33. The method of claim 32, further comprising:

determining the first state of the identified plurality of portions based at least in part on the identifying the plurality of portions, wherein executing the truncated read

operation is based at least in part on determining the first state of the identified plurality of portions.

34. The method of claim 32, wherein executing the truncated read operation comprises:

maintaining the plurality of portions in the first state based at least in part on determining the first state of the identified plurality of portions.

35. The method of claim 32, further comprising:

selecting the truncated read operation, the truncated read operation being a part of a full read operation, wherein executing the truncated read operation is based at least in part on selecting the truncated read operation.

36. An apparatus, comprising:

means for identifying a part of a read command for setting at least one portion of a memory array to a temporary state;

means for identifying the at least one portion of the memory array based at least in part on the part of the read command; and

means for executing the part of the read command on the at least one portion of the memory array based at least in part on identifying the at least one portion of the memory array.

37. The apparatus of claim 36, further comprising:

means for performing a read recovery part of a read operation, wherein the read operation comprises the read recovery part and a data sense part.

38. The apparatus of claim 36, further comprising:

means for increasing a voltage applied to all word lines associated with the at least one portion to a first voltage above a threshold voltage of memory cells of the at least one portion;

means for increasing a voltage applied to at least one gate of at least one select gate device of the at least one portion to a second voltage above a second threshold voltage of the at least one select gate device; and

means for setting a voltage applied to a source, a drain, a bit line, or a combination thereof, of the at least one portion to a third voltage.

39. The apparatus of claim 38, further comprising:

means for decreasing the voltage applied to all word lines from the first voltage to a fourth voltage based at least in part on achieving the first voltage; and

means for decreasing the voltage applied to the at least one gate of the at least one select gate device from the second voltage to below the second threshold voltage based at least in part on decreasing the voltage applied to all word lines.

40. The apparatus of claim 36, further comprising:

means for retaining a word line to a channel potential difference of the memory cells at a level that is lower than a voltage of a source, a drain, a bit line, or a combination thereof of the memory cells after executing the part of the read command.

41. The apparatus of claim 36, further comprising:

means for determining a duration since a last read operation for the at least one portion, wherein identifying the at least one portion of the memory array is based at least in part on determining the duration.

42. The apparatus of claim 36, further comprising:

means for determining a mode of executing the part of the read command, wherein executing the part of the read command is based at least in part on determining the mode.

43. The apparatus of claim 42, further comprising:

means for identifying a product design identification of the memory array, wherein determining the mode comprises determining a number of portions of the memory array on which the part of the read command is to be executed based at least in part on the product design identification.

44. The apparatus of claim 43, further comprising:

means for executing the part of the read command concurrently on a plurality of portions of the memory array based at least in part on determining the number of portions.

45. The apparatus of claim 36, further comprising:

means for receiving a request to perform the read command; and

means for initiating the part of the read command based at least in part on receiving the request.

46. The apparatus of claim 45, further comprising:

means for identifying a set feature and a trim condition associated with the part of the read command; and

means for determining a configuration for executing the part of the read command based at least in part on identifying the set feature and the trim condition, wherein executing the part of the read command is based at least in part on determining the configuration.

47. An apparatus, comprising:

means for initiating a reset read command that sets at least one portion of a memory array into a temporary state;

means for applying, to all word lines associated with the at least one portion, a voltage that increases to a first voltage above a threshold voltage of memory cells of the at least one portion based at least in part on the initiating;

means for applying, to at least one gate of at least one select gate device of the at least one portion, a voltage that increases to a second voltage above a second threshold voltage of the at least one select gate device based at least in part on the initiating; and

means for setting a node of the at least one portion to a third voltage based at least in part on the initiating.

48. The apparatus of claim 47, further comprising:

means for initiating a transition of the at least one portion into the temporary state.

49. The apparatus of claim 47, further comprising:

means for maintaining the at least one portion in the temporary state.

50. The apparatus of claim 47, further comprising:

means for decreasing the voltage applied to all word lines associated with the at least one portion from the first voltage to a fourth voltage based at least in part on achieving the first voltage; and

means for decreasing the voltage applied to the at least one gate of the at least one select gate device of the at least one portion from the second voltage to below the second threshold voltage based at least in part on decreasing the voltage applied to all word lines.

51. The apparatus of claim 47, further comprising:

means for applying the voltage that increases to the first voltage above the threshold voltage of the memory cells;

means for applying the voltage that increases to the second voltage above the second threshold voltage of the at least one select gate device; and

means for setting the node of the at least one portion to the third voltage.

52. An apparatus, comprising:

means for identifying a part of a read command for setting at least one portion of a memory array into a temporary state;

means for identifying the at least one portion of the memory array based at least in part on the part of the read command; and

means for executing the part of the read command on the at least one portion of the memory array based at least in part on identifying the at least one portion of the memory array.

53. The apparatus of claim 52, further comprising:

means for determining a number of portions on which the part of the read command is to be executed concurrently based at least in part on a product design identification of the memory array, wherein executing the part of the read command is based at least in part on determining the number of portions.

54. The apparatus of claim 52, further comprising:

means for receiving a request from a processor to execute the part of the read command, wherein identifying the part of the read command is based at least in part on the received request.

55. An apparatus, comprising:

means for initiating a reset read command that sets at least one portion of a memory array into a temporary state;

means for increasing a voltage applied to all word lines associated with the at least one portion to a first voltage above a threshold voltage of memory cells of the at least one portion based at least in part on the initiating;

means for increasing a voltage applied to at least one gate of at least one select gate device of the at least one portion to a second voltage above a second threshold voltage of the at least one select gate device based at least in part on the initiating; and

means for setting a node of the at least one portion to a third voltage based at least in part on the initiating.

56. The apparatus of claim 55, further comprising:

means for initiating a transition of the at least one portion into the temporary state or maintaining the at least one portion in the temporary state.

57. The apparatus of claim 55, further comprising:

means for decreasing the voltage applied to all word lines associated with the at least one portion from the first voltage to a fourth voltage based at least in part on achieving the first voltage; and

means for decreasing the voltage applied to the at least one gate of the at least one select gate device of the at least one portion from the second voltage to below the second threshold voltage based at least in part on decreasing the voltage applied to all word lines.

58. The apparatus of claim 55, further comprising:

means for identifying a set feature and a trim condition associated with the reset read command, wherein the set feature and the trim condition are set by a processor; and means for determining a configuration for performing the reset read command based at least in part on identifying the set feature and the trim condition.

59. An apparatus, comprising:

means for receiving a request to perform a part of a read command on a memory array;

means for identifying a plurality of portions of the memory array based at least in part on the received request; and

means for executing a truncated read operation concurrently on the plurality of portions to set the plurality of portions in a first state based at least in part on identifying the plurality of portions.

60. The apparatus of claim 59, further comprising:

means for determining the first state of the identified plurality of portions based at least in part on the identifying the plurality of portions, wherein executing the truncated read operation is based at least in part on determining the first state of the identified plurality of portions.

61. The apparatus of claim 59, further comprising:

means for maintaining the plurality of portions in the first state based at least in part on determining the first state of the identified plurality of portions.

62. The apparatus of claim 59, further comprising:

means for selecting the truncated read operation, the truncated read operation being a part of a full read operation, wherein executing the truncated read operation is based at least in part on selecting the truncated read operation.