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1. (WO2019045999) PROVIDING EFFICIENT RECURSION HANDLING USING COMPRESSED RETURN ADDRESS STACKS (CRASS) IN PROCESSOR-BASED SYSTEMS
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What is claimed is:

1 , A processor-based system for efficiently handling recursion, comprising:

a branch prediction circuit comprising:

a compressed return address stack (CRAS) comprising a plurality of CRAS entries, each CRAS entry of the plurality of CRAS entries comprising an address field and a counter field, and

a CRAS top-of-stack (TOS) index to indicate a top CRAS entry of the plurality of CRAS entries of the CRAS;

the branch prediction circuit configured to, upon execution of a call instruction by an execution pipeline of the processor-based system:

determine a return address corresponding to the call instruction; determine whether the return address matches the address field of the top CRAS entry indicated by the CRAS TOS index; and

responsive to determining that the return address matches the address field of the top CRAS entry, increment the counter field of the top CRAS entry,

2, The processor-based system of claim 1, wherein the branch prediction circuit is further configured to, responsive to determining that the return address does not match the address field of the top CRAS entry:

update the CRAS TOS index to indicate a next CRAS entry of the plurality of

CRAS entries of the CRAS as the top CRAS entry;

store the return address in the address field of the top CRAS entry; and store a value of zero (0) in the counter field of the top CRAS entry.

3, The processor-based system of claim 2, wherein the branch prediction circuit is further configured to, upon detection of a return instruction by the execution pipeline of the processor-based system:

provide a content of the address field of the top CRAS entry indicated by the CRAS TOS index to the execution pipeline as a return address for the return instruction;

determine whether the counter field of the top CRAS entry has a value greater than zero (0);

responsive to determining that the counter field of the top CRAS entry has a value greater than zero (0), decrement the value of the counter field of the top CRAS entry; and

responsive to determining that the counter field of the top CRAS entry does not have a value greater than zero (0), update the CRAS TOS index to indicate a previous CRAS entry of the plurality of CRAS entries of the CRAS as the top CRAS entry.

The processor-based system of claim 3, wherein the branch prediction circuit r comprises:

a call pattern table (CPT) comprising a plurality of CPT entries, each CPT entry of the plurality of CPT entries comprising an address index stack and a counter field;

a CPT TOS index indicating a top return address within the address index stack of a top CPT entry of the plurality of CPT entries of the CPT;

the branch prediction circuit further configured to, upon execution of the call instruction by the execution pipeline of the processor-based system: append an index of the return address in the CRAS to the address index stack of the top CPT entry of the plurality of CPT entries of the CPT indicated by the CPT TOS index; and

update the CPT TOS index to indicate the index of the return address within the address index stack of the top CPT entry as the top return address.

5. The processor-based system of claim 4, wherein the branch prediction circuit is further configured to:

determine whether the address index stack of the top CPT entry indicated by the CPT TOS index matches the address index stack of a previous CPT entry of the plurality of CPT entries of the CPT; and

responsive to determining that the address index stack of the top CPT entry indicated by the CPT TOS index matches the address index stack of a previ ous CPT entry of the plurality of CPT entries of the CPT:

increment the counter field of the previous CPT entry; and update the CPT TOS index to indicate the last index within the address index stack of the previous CPT entry as the top return address.

6. The processor-based system of claim 5, wherein the branch prediction circuit is further configured to:

determine whether the address index stack of the top CPT entry contains a repeated pattern;

responsive to determining that the address index stack of the top CPT entry contains a repeated pattern:

collapse the address index stack into a single occurrence of the repeated pattern; and

increment the counter field of the top CPT entry.

7. The processor-based system of claim 6, wherein the branch prediction circuit is further configured to, upon detection of the return instruction by the execution pipeline of the processor-based system:

provide the top return address indicated by the CPT TOS index to the execution pipeline as the return address for the return instruction;

determine whether the CPT TOS index indicates a first-added index in the address index stack of the top CPT entry;

responsive to determining that the CPT TOS index indicates a first-added index in the address index stack of the top CPT entry :

determine whether the counter field of the top CPT entry has a value greater than zero (0);

responsive to determining that the counter field of the top CPT entry has a value greater than zero (0):

decrement the value of the counter field of the top CPT entry; and update the CPT TOS index to indicate a last-added index in the address index stack of the top CPT entry as the top return address; and

responsive to determining that the counter field of the top CPT entry does not have a value greater than zero (0), update the CPT TOS index to indicate a last-added index within the address index stack of a previous CPT entry as the top return address; and responsive to determining that the CPT TOS index does not indicate a first- added address in the address index stack of the top CPT entry, update the CPT TOS index to indicate a previous index within the address index stack of the top CPT entry as the top return address.

8. The processor-based system of claim 1 integrated into an integrated circuit (IC).

9. The processor-based system of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device, a fixed location data unit, a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet, a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television, a tuner, a radio, a satellite radio, a music player, a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile, a vehicle component; avionics systems; a drone; and a muiticopter.

10. A method for efficiently handling recursion, comprising:

determining, by a branch prediction circuit of a processor-based system, a return address corresponding to a call instruction executed by an execution pipeline of the processor-based system,

determining whether the return address matches an address field of a top compressed return address stack (CRAS) entry of a plurality of CRAS entries of a CRAS indicated by a CRAS top-of-staek (TOS) index, wherein each CRAS entry of the plurality of CRAS entries comprises an address field and a counter field; and

responsive to determining that the return address matches the address fi eld of the top CRAS entry, incrementing the counter field of the top CRAS entry.

11. The method of claim 10, further comprising, responsive to determining that the return address does not match the address field of the top CRAS entry:

updating the CRAS TOS index to indicate a next CRAS entry of the plurality of

CRAS entries of the CRAS as the top CRAS entry;

storing the return address in the address fi eld of the top CRA S entry; and storing a value of zero (0) in the counter field of the top CRAS entry.

12. The method of claim 1 1 , further comprising, upon detection of a return instruction by the execution pipeline of the processor-based system:

providing a content of the address field of the top CRAS entry indicated by the CRAS TOS index to the execution pipeline as a return address for the return instruction;

determining whether the counter field of the top CRAS entry has a value greater than zero (0), and

responsive to determining that the counter field of the top CRAS entry has a value greater than zero (0), decrementing the value of the counter field of the top CRAS entry.

13. The method of claim 12, further comprising, responsive to determining that the counter field of the top CRAS entry does not have a value greater than zero (0), updating the CRAS TOS index to indicate a previous CRAS entry of the plurality of CRAS entries of the CRAS as the top CRAS entry,

14. The method of claim 13, further comprising, upon execution of the call instruction by the execution pipeline of the processor-based system:

appending an index of the return address in the CRAS to an address index stack of a top call pattern table (CPT) entry of a plurality of CPT entries of a CPT indicated by a CPT TOS index, each CPT entry of the plurality of CPT entries comprising an address index stack and a counter field; and updating the CPT TOS index to indicate the return address within the address index stack of the top CPT entry as a top return address.

15. The method of claim 14, further comprising:

determining whether the address index stack of the top CPT entry indicated by the CPT TOS index matches the address index stack of a previous CPT entry of the plurality of CPT entries of the CPT; and

responsive to determining that the address index stack of the top CPT entry indicated by the CPT TOS index matches the address index stack of a previous CPT entry of the plurality of CPT entries of the CPT:

incrementing the counter field of the previous CPT entry, and updating the CPT TOS index to indicate a first-added index within the address index stack of the previous CPT entry as the top return address.

The method of claim 15, further comprising:

determining whether the address index stack of the top CPT entry contains a repeated pattern;

responsive to determining that the address index stack of the top CPT entry contains a repeated pattern:

collapsing the address index stack into a single occurrence of the repeated pattern; and

incrementing the counter field of the top CPT entry.

17. The method of claim 16, further comprising, upon detection of the return instruction by the execution pipeline of the processor-based system:

providing the top return address indicated by the CPT TOS index to the execution pipeline as the return address for the return instruction;

determining whether the CPT TOS index indicates a first-added index in the address index stack of the top CPT entry; and

responsive to determining that the CPT TOS index indicates a first-added index in the address index stack of the top CPT entry:

determining whether the counter field of the top CPT entry has a value greater than zero (0);

responsive to determining that the counter field of the top CPT entry has a value greater than zero (0):

decrementing the value of the counter field of the top CPT entry;

and

updating the CPT TOS index to indicate a last-added index in the address index stack of the top CPT entry as the top return address.

18. The method of claim 17, further comprising, responsive to determining that the counter field of the top CPT entry does not have a value greater than zero (0), updating the CPT TOS index to indicate a last-added index within the address index stack of a previous CPT entry as the top return address.

19. The method of claim 18, further comprising, responsive to determining that the CPT TOS index does not indicate a first-added index in the address index stack of the top CPT entry, updating the CPT TOS index to indicate a previous index within the address index stack of the top CPT entry as the top return address.

20. A processor-based system for efficiently handling recursion, comprising:

a means for determining a return address corresponding to a call instruction executed by an execution pipeline of the processor-based system;

a means for determining whether the return address matches an address field of a top compressed return address stack (CRAS) entry of a plurality of CRAS entries of a CRAS indicated by a CRAS top-of-stack (TOS) index, wherein each CRAS entry of the plurality of CRAS entries comprises an address field and a counter field; and

a means for incrementing the counter field of the top CRAS entry, responsive to determining that the return address matches the address field of the top CRAS entry.

21. A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to: determine a return address corresponding to a call instruction executed by an execution pipeline of a processor-based system;

determine whether the return address matches an address field of a top compressed return address stack (CRAS) entry of a plurality of CRAS entries of a CRAS indicated by a CRAS top-of-stack (TOS) index, wherein each CRAS entry of the plurality of CRAS entries comprises an address field and a counter field; and

responsive to determining that the return address matches the address field of the top CRAS entry, increment the counter field of the top CRAS entry.

22. The non-transitory computer-readable medium of claim 21 having stored thereon computer-executable instructions which, when executed by a processor, further cause the processor to, responsive to determining that the return address does not match the address field of the top CRAS entry:

update the CRAS TOS index to indicate a next CRAS entry of the plurality of

CRAS entries of the CRAS as the top CRAS entry;

store the return address in the address field of the top CRAS entry; and store a value of zero (0) in the counter field of the top CRAS entry.

23. The non-transitory computer-readable medium of claim 22 having stored thereon computer-executable instructions which, when executed by a processor, further cause the processor to, upon detection of a return instruction by the execution pipeline of the processor-based system:

provide a content of the address field of the top CRAS entry indicated by the CRAS TOS index to the execution pipeline as a return address for the return instruction;

determine whether the counter field of the top CRAS entry has a value greater than zero (0); and

responsive to determining that the counter field of the top CRAS entry has a value greater than zero (0), decrement the value of the counter field of the top CRAS entry.

24. The non-transitory computer-readable medium of claim 23 having stored thereon computer-executable instructions which, when executed by a processor, further cause the processor to, responsive to determining that the counter field of the top CRAS entry does not have a value greater than zero (0), update the CRAS TOS index to indicate a previous CRAS entry of the plurality of CRAS entries of the CRAS as the top CRAS entry.

25. The non-transitory computer-readable medium of claim 24 having stored thereon computer-executable instructions which, when executed by a processor, further cause the processor to, upon execution of the call instruction by the execution pipeline of the processor-based system :

append an index of the return address in the CRAS to an address index stack of a top call pattern table (CPT) entry of a plurality of CPT entries of a CPT indicated by a CPT TOS index, each CPT entry of the plurality of CPT entries comprising an address index stack and a counter field; and update the CPT TOS index to indicate the return address within the address index stack of the top CPT entry as a top return address.

26. The non-transitory computer-readable medium of claim 25 having stored thereon computer-executable instructions which, when executed by a processor, further cause the processor to:

determine whether the address index stack of the top CPT entry indicated by the CPT TOS index matches the address index stack of a previous CPT entry of the plurality of CPT entries of the CPT; and

responsive to determining that the address index stack of the top CPT entry indicated by the CPT TOS index matches the address index stack of a previous CPT entry of the plurality of CPT entries of the CPT:

increment the counter field of the previous CPT entry; and update the CPT TOS index to indicate a first-added index within the address index stack of the previous CPT entry as the top return address,

27. The non-transitory computer-readable medium of claim 26 having stored thereon computer-executable instructions which, when executed by a processor, further cause the processor to:

determine whether the address index stack of the top CPT entry contains a repeated pattern; and

responsive to determining that the address index stack of the top CPT entry contains a repeated pattern:

collapse the address index stack into a single occurrence of the repeated pattern; and

increment the counter field of the top CPT entry.

28. The non-transitory computer-readable medium of claim 27 having stored thereon computer-executable instructions which, when executed by a processor, further cause the processor to, upon detection of the return instruction by the execution pipeline of the processor-based system:

provide the top return address indicated by the CPT TOS index to the execution pipeline as the return address for the return instruction;

determine whether the CPT TOS index indicates a first-added index in the address index stack of the top CPT entry; and

responsive to determining that the CPT TOS index indicates a first-added index in the address index stack of the top CPT entry:

determine whether the counter field of the top CPT entry has a value greater than zero (0); and

responsive to determining that the counter field of the top CPT entry has a value greater than zero (0):

decrement the value of the counter field of the top CPT entry; and update the CPT TOS index to indicate a last-added index in the address index stack of the top CPT entry as the top return address.

29. The non-transitory computer-readable medium of claim 28 having stored thereon computer-executable instructions which, when executed by a processor, further cause the processor to, responsive to determining that the counter field of the top CPT entry does not have a value greater than zero (0), update the CPT TOS index to indicate a last-added index within the address index stack of a previous CPT entry as the top return address.

30. The non-transitory computer-readable medium of claim 29 having stored thereon computer-executable instructions which, when executed by a processor, further cause the processor to, responsive to determining that the CPT TOS index does not indicate a first-added index in the address index stack of the top CPT entn,', update the CPT TOS index to indicate a previous index within the address index stack of the top CPT entry as the top return address.