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1. (WO2019005166) METHOD AND APPARATUS FOR VECTORIZING HISTOGRAM LOOPS
ملاحظة: نص مبني على عمليات التَعرف الضوئي على الحروف. الرجاء إستخدام صيغ PDF لقيمتها القانونية

CLAIMS

What is claimed is:

1. A method for executing an instruction, the method comprising:

decoding an instruction by a decode circuit, the instruction comprising an opcode, a destination vector identifier, a source vector identifier, and an immediate value; and

executing the decoded instruction by an execution circuit by:

for each data element position of a source vector identified by the source vector identifier,

determining a number of matching data element positions in the source vector storing a same data value as stored at the data element position, the matching data element positions located between the data element position and a least significant data element position of the source vector, and

storing, in a corresponding data element position of a destination vector identified by the destination vector identifier, a value representing the number of matching data element positions.

2. The method of claim 1, wherein the stored value representing the number of matching data element positions is a sum of the number of matching data element positions and the immediate value.

3. The method of claim 1, wherein the destination vector identifier and the source vector identifier identify storage locations.

4. The method of claim 1, wherein a size of data elements in the source vector identified by the source vector identifier is one of byte, word, doubleword, and quadword.

5. The method of claim 1, wherein the source vector identifier is a first source vector identifier and the source vector is a first source vector, and wherein the instruction further comprises a second source vector identifier, and wherein the stored value represents a sum of the number of matching data element positions, a corresponding data element position of a second source vector identified by the second source vector identifier, and the immediate value storing the value representing the number of matching data element positions further includes adding the value to a corresponding data element position of a second source vector identified by the second source vector identifier.

6. A processor for executing an instruction, the processor comprising:

a decode circuit to decode an instruction, the instruction comprising an opcode, a destination vector identifier, a source vector identifier, and an immediate value; and

an execution circuit to execute the decoded instruction to, for each data element position of a source vector identified by the source vector identifier,

determine a number of matching data element positions in the source vector storing a same data value as stored at the data element position, the matching data element positions located between the data element position and a least significant data element position of the source vector, and

store, in a corresponding data element position of a destination vector identified by the destination vector identifier, a value representing the number of matching data element positions.

7. The processor of claim 6, wherein the stored value representing the number of matching data element positions is a sum of the number of matching data element positions and the immediate value.

8. The processor of claim 6, wherein the destination vector identifier and the source vector identifier identify storage locations.

9. The processor of claim 6, wherein a size of data elements in the source vector identified by the source vector identifier is one of byte, word, doubleword, and quadword.

10. The processor of claim 6, wherein the source vector identifier is a first source vector identifier and the source vector is a first source vector, and wherein the instruction further comprises a second source vector identifier, and wherein the stored value represents a sum of the number of matching data element positions, a corresponding data element position of a second source vector identified by the second source vector identifier, and the immediate value.

11. An apparatus to execute an instruction, the apparatus comprising:

means for decoding an instruction, the instruction comprising an opcode, a destination vector identifier, a source vector identifier, and an immediate value; and

means for executing the decoded instruction to, for each data element position of a source vector identified by the source vector identifier,

determine a number of matching data element positions in the source vector storing a same data value as stored at the data element position, the matching data element positions located between the data element position and a least significant data element position of the source vector, and

store, in a corresponding data element position of a destination vector identified by the destination vector identifier, a value representing the number of matching data element positions.

12. The apparatus of claim 11, wherein the stored value representing the number of matching data element positions is a sum of the number of matching data element positions and the immediate value.

13. The apparatus of claim 11, wherein the destination vector identifier and the source vector identifier identify storage locations.

14. The apparatus of claim 11, wherein a size of data elements in the source vector identified by the source vector identifier is one of byte, word, doubleword, and quadword.

15. The apparatus of claim 11, wherein the source vector identifier is a first source vector identifier and the source vector is a first source vector, and wherein the instruction further comprises a second source vector identifier, and wherein the stored value represents a sum of the number of matching data element positions, a corresponding data element position of a second source vector identified by the second source vector identifier, and the immediate value.

16. A non-transitory machine-readable medium containing instructions that, when performed by a processor, cause the performance of operations comprising:

fetching an instruction from a code storage by a fetch circuit, the instruction comprising an opcode, a destination vector identifier, a source vector identifier, and an immediate value;

decoding the fetched instruction by a decode circuit; and

executing the decoded instruction by an execution circuit on a source vector identified by the source vector identifier to, for each data element position of the source vector,

determine a number of matching data element positions in the source vector storing a same data value as stored at the data element position, the matching data element positions located between the data element position and a least significant data element position of the source vector, and

store, in a corresponding data element position of a destination vector identified by the destination vector identifier, a value representing the number of matching data element positions.

17. The non-transitory machine-readable medium of claim 16, wherein the stored value representing the number of matching data element positions is a sum of the number of matching data element positions and the immediate value.

18. The non-transitory machine-readable medium of claim 16, wherein the destination vector identifier and the source vector identifier identify storage locations.

19. The non-transitory machine-readable medium of claim 16, wherein a size of data elements in the source vector identified by the source vector identifier is one of byte, word, doubleword, and quadword.

20. The non-transitory machine-readable medium of claim 16, wherein the source vector identifier is a first source vector identifier and the source vector is a first source vector, and wherein the instruction further comprises a second source vector identifier, and wherein the stored value represents a sum of the number of matching data element positions, a corresponding data element position of a second source vector identified by the second source vector identifier, and the immediate value.