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1. (WO2019005148) FLOATING GATE TRANSISTOR
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FLOATING GATE TRANSISTOR

BACKGROUND

[0001] Power-gating is a known technique to reduce power consumption (e.g., leakage power consumption) of integrated circuits (ICs) or logic blocks during periods of inactivity. Yet, the use of power-gating is limited because of the performance impact of restoring memory state as the voltage supply is restored to a logic block. Many products, such as servers, are not able to fully take advantage of core power-gating for this reason.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1 illustrates a transistor model of a floating-gate transistor, according to some embodiments of the disclosure.

[0004] Fig. 2 illustrates a top view of a layout of the floating-gate transistor, according to some embodiments of the disclosure.

[0005] Fig. 3 illustrates a cross-section of an active region of the floating-gate transistor, according to some embodiments of the disclosure.

[0006] Fig. 4 illustrates a cross-section of a control-gate of the floating-gate transistor, according to some embodiments of the disclosure.

[0007] Fig. 5 illustrates a plot showing the memory effect of the floating-gate transistor, according to some embodiments of the disclosure.

[0008] Fig. 6 illustrates a memory -bit cell with fully integrated floating-gate transistors for saving and restoring data from and to storage nodes during power-gating, respectively, according to some embodiments of the disclosure.

[0009] Figs. 7A-B illustrate a layout of the memory -bit-cell with fully integrated floating-gate transistors, according to some embodiments of the disclosure.

[0010] Fig. 8 illustrates a plot showing gate leakage that provides write current, according to some embodiments.

[0011] Fig. 9 illustrates a plot showing read current over retention time, according to some embodiments.

[0012] Fig 10 illustrates top view of a layout of floating-gate transistor 100, according to some embodiments of the disclosure.

[0013] Fig. 11 illustrates an alternate memory bit-cell with fully integrated floating-gate transistors for saving and restoring data to storage nodes during power-gating, according to some embodiments of the disclosure.

[0014] Fig. 12 illustrates a smart device or a computer system or a SoC (System-on- Chip) with the floating-gate transistor, according to some embodiments.

DETAILED DESCRIPTION

[0015] One way to retain state when power-gating a logic block of an IC chip is to use an embedded flash on die. This process may have high process cost (e.g., 8 to 10 masks), may require high voltage for programming the flash, and may provide retention

characteristics that exceed requirements for some applications. Another way to retain state when power-gating a logic block of an IC chip is to use micro-code based save-restore flows. This scheme may use data movement from a static random access memory (SRAM), which may take significant time (e.g., 18 μβ) and energy. Another scheme for retaining state when power-gating is to use distributed retention registers powered by an Always-On (AON) power supply. However, logic blocks with multiple power supply domains, including AON power domains, may have area and performance overheads.

[0016] Some embodiments here describe a floating-gate scheme that is built on a complementary metal oxide semiconductor (CMOS) process without special memory-specific processing steps. For example, to retain a state of a memory storage node, specialized non-volatile memory devices such as magnetic tunneling junction (MTJ) are not needed. In some embodiments, a standard metal gate, which is used for other transistors or devices of an IC, is used to form a floating-gate device. In some embodiments, no Ohmic contact is made to the floating-gate in the layout of the floating gate.

[0017] For example, the floating-gate is capacitively charged without direct contact.

In some embodiments, the means for capacitively charging the floating-gate is a contact layer (e.g., a conductive metal layer used for near active region interconnections or contacts). As such, the contact layer performs a function of a control gate which capacitively charges or discharges the floating-gate. One example of the contact layer is a trench contact layer (also referred to as TCN) which forms the TCN gate (also referred to as the control-gate). In some embodiments, the capacitance from the TCN-gate pitches forms the capacitance between the control-gate and the floating-gate.

[0018] There are many technical effects of the various embodiments. For example, the floating-gate transistor may enable increased power-gating use with memory or register that retain state. The floating-gate transistor of some embodiments can reduce the time for save-restore flows compared to the micro-code based save-restore flows. For example, the floating-gate transistor of some embodiments can reduce the save-restore time by 40 % over the micro-code based save-restore flows. The floating-gate transistor based power-gating solutions may also reduce the circuit and power delivery overhead of conventional AON retention registers. Other technical effects will be evident from the various embodiments and figures.

[0019] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0020] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0021] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0022] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0023] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0024] Fig. 1 illustrates transistor model 100 of a floating-gate transistor, according to some embodiments of the disclosure. Transistor model 100 comprises a control-gate node 101, floating-gate capacitor 102, floating-gate node 103, source node 104, drain node 105, bulk (body or substrate) node 106. In this example, a p-type floating-gate transistor is shown. However, a similar model can be made for an n-type floating-gate transistor using the same principles. In some embodiments, the control-gate node 101 is capacitively coupled to the floating-gate node 103 via capacitor 102. For example, there is no ohmic contact between floating-gate node 103 and control-gate node 101. The capacitance of floating-gate capacitor 102 depends on the distance of the control-gate node 101 from the floating-gate node 103. In some embodiments, control-gate node 101 is formed from TCN contact material. In some embodiments, the TCN contact material includes one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

[0025] Plot 120 shows the control-gate voltage on node 101 over time-points tO, tl, t2, and t3. Plot 130 shows the corresponding floating-gate voltage on node 103, which is capacitively coupled to node 103 from node 101 via coupling capacitor 102. Plot 140 shows the corresponding leakage current. Low control-gate voltage between times t2 and t3 results in low leakage retention. In this example, source node 104, drain node 105, and body node 106 is tied to ground (Vss). In some embodiments, gate oxide leakage currents provide a charging current used for writing the floating-gate transistor and leakage currents that limits retention. The retention duration of the floating-gate transistor may not be as long as a nonvolatile MTJ, but is long enough for enabling short power-gating events. For example, the retention duration of the floating-gate transistor is about 100 milli-seconds (ms) which is long enough for various power-gating scenarios.

[0026] Fig. 2 illustrates top view 200 of a layout of floating-gate transistor 100, according to some embodiments of the disclosure. It is pointed out that those elements of

Fig. 2 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0027] In some embodiments, an active region 201 (e.g., n-diffusion or p-diffusion region, depending on the type or transistor (p-type or n-type) and the process technology) is defined according to the desired length and width of the floating-gate transistor 100. In some embodiments, source and drain regions are formed by known methods (e.g., doped regions on either sides of gate 202).

[0028] In some embodiments, the source and drain regions are contacted via contact materials 203 and 204, respectively. In this example, contact material 203 forms the source region contact while contact material 204 forms the drain region contact. A person skilled in the art would appreciate that source and drain regions may be identical regions, and the labels of "source" and "drain" are attributed according to the potentials applied to those regions.

[0029] In some embodiments, gate 202 is any type of gate that the process technology node is using. For example, floating-gate transistor 100 may be a FinFET (Tri-gate transistor) or a regular planar transistor. The various embodiments for forming floating-gate transistor 100 is applicable to any type of transistor provided by the process technology node.

[0030] In some embodiments, gate 202 is much wider (W) than its length (L). For example, W is greater than L. In some embodiments, source and drain contact materials 203 and 204, respectively, do not extend along the entire width (W) of gate 202. For example, source and drain contact materials 203 and 204, respectively, are disposed within active region 201 while gate 202 may have a width that extends beyond active region 201. In some embodiments, material used for source and drain contacts 203 and 204, respectively, is also used to form contact nodes 205 and 206, respectively. In some embodiments, contact material 205 is deposited along gate 202, without touching gate 202, such that contact material 205 extends along the width W of gate 201 while leaving a gap or discontinuity 'D' between source contact material 203 and contact material 205. As such, no ohmic contact is made between contact material 205 and gate 202.

[0031] In some embodiments, contact material 206 is deposited along gate 202, without touching gate 202, such that contact material 206 extends along the width W of gate 201 while leaving a gap or discontinuity 'D' between drain contact material 204 and contact material 206. As such, no ohmic contact is made between contact material 206 and gate 202. In some embodiments, contact material 206 is deposited along gate 202, without touching gate 202, such that contact material 206 extends along the width W of gate 201 while leaving a gap or discontinuity 'D' between source contact material 203 and contact material 206. As such, no ohmic contact is made between contact material 206 and gate 202.

[0032] In some embodiments, contact materials 203, 204, 205, and 206 are deposited at the same time and formed of the same material. In some embodiments, contact materials 205 and 206 are electrically coupled together to form a capacitor around floating-gate 202. In some embodiments, near or at the end of contact material 205, a contact or via 207 is formed. In some embodiments, near or at the end of contact material 206, a contact or via 208 is formed. In some embodiments, another metal layer 209 is deposited over via/contact 207 and 208 such that contact material 205 and 206 is electrically coupled and wraps around gate 202. In some embodiments, layer 209 is a metal 0 (e.g., M0) layer. In some embodiments, via/contacts 207 and 208 are not needed, and the same material used for contact material 205 and 206 can be used to couple the ends contact material 205 and 206 instead of separate metal layer 209. In some embodiments, via/contacts 207 and 208 are not needed, and metal layer 209 can be used to couple the ends contact material 205 and 206. In some

embodiments, the metal layer 209 is a gate contact trench (GCN) which couples TCN contact material 205 and 206 without via/contacts 207 and 208.

[0033] In some embodiments, layer 209 is also formed of the same material as contact material used for 203, 204, 205, and 206. For example, the material includes one of: includes one of: Tungsten, Tantalum, Titanium, Copper, Nickel, or Aluminum, or a combination of them. In some embodiments, layer 209 may electrically connect to 207 and 208 directly without need for via 207 and via 208. Cross-sectional view along cross-sections AA and BB are illustrated with reference to Figs. 3-4, respectively.

[0034] Fig. 3 illustrates cross-section 300 (AA) of an active region of the floating-gate transistor, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Cross-section 300 illustrates active region 201 formed over substrate 301 (e.g., silicon, polysilicon, bulk silicon, etc.) or oxide layer 301. In some embodiments, active region 201 is a well region (e.g., p-well or n-well). For example, active region 201 is a lightly doped n-type or lightly doped p-type region, depending on whether a p-type or n-type floating-gate transistor is being formed.

[0035] In some embodiments, source contact material 203 is formed over a source region 303, which may be a highly doped region (e.g., highly doped n-type or highly doped p-type region). In some embodiments, drain contact material 204 is formed over a drain

region 304, which may be a highly doped region (e.g., highly doped n-type or highly doped p-t pe region). Conventional dopants such as Arsenic, Phosphorous, Boron, etc., may be used for doping purposes. The length 'L' of the floating-gate 202 is a distance between the source and drain regions 303 and 304, respectively.

[0036] Fig. 4 illustrates cross-section 400 (BB) of a control-gate of the floating-gate transistor, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 4 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Cross-section 400 shows that the gap between floating-gate 202 and contact regions 205/206 provides capacitance 102 which is used to charge or discharge floating gate 202. As such, contact regions 205/206 together form control node 101 (also referred to as control-gate 101).

[0037] In some embodiments, multiple segments of gate material are connected. In some embodiments multiple segments of contact material may be connected. In some embodiments, the connected gate material segments are placed near the multiple contact segments providing a capacitance between the contact segments and gate segments. In some embodiments the contact segments and gate segments are interdigitated.

[0038] Fig. 5 illustrates plot 500 showing the memory effect of the floating-gate transistor, according to some embodiments of the disclosure. Here, the x-axis is voltage on control-gate 101 while the y-axis is channel current in μΑ/FinFET. In some embodiments, when floating-gate transistor 100 is programmed to have low-Vt (e.g., low threshold) it produces the curve 501 , and when floating-gate transistor 100 is programmed to have high-Vt (e.g., high threshold) it produces the curve 502. As such, floating-gate transistor 100 can be used for storing or is programmed for storing a logic high (1) or logic low (0).

[0039] Floating gate 103 may be programmed by applying a voltage to control gate

101, source 104 and drain 105. Control gate capacitance 102 will cause the floating gate 103 to capacitively couple to the control gate 101. Thus, changing the control gate to source voltage or control gate to drain voltage will cause a voltage to develop across the gate oxide of transistor 100. Gate leakage currents will increase exponentially with increasing voltage magnitude and charge the floating gate. Gate leakage currents will decrease exponentially with decreasing voltage magnitude and reduce leakage currents that will dissipate the stored charge representing the retained state. In some embodiments, applying a rising signal transitioning from ground (Vss) to supply voltage (Vdd) to the control gate and Vss to the source and/or drain, will couple the floating gate 103 to a rising voltage and cause the floating gate voltage to increase.

[0040] With a positive voltage across the gate oxide, leakage currents will discharge the floating gate 103. In some embodiments, applying a falling signal transitioning from Vdd to Vss to the control gate 101 and Vdd to the source 104 and/or drain 105, will couple the floating gate 103 to a falling voltage and cause the floating gate voltage to decrease. In some embodiments, applying a positive voltage to the source 104 and/or drain 105 relative the floating gate 103 will cause the floating gate 103 to charge. In some embodiments, applying a negative voltage to the source 104 and/or drain 105 relative the floating gate 103 will cause the floating gate 103 to discharge. With a positive voltage across the gate oxide, leakage currents will discharge the floating gate 103. With a negative voltage across the gate oxide, leakage currents will charge the floating gate 103. In some embodiments the rate of charging or discharging may be exponentially related to the magnitude of the voltage across the gate oxide.

[0041] Fig. 6 illustrates a memory-bit cell 600 with fully integrated floating-gate transistors for saving and restoring data to storage nodes during power-gating, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0042] In some embodiments, memory-bit cell 600 comprises p-type access-devices

MP1 and MP2, cross-coupled inverters comprising n-type transistors MN1 and MN2, and p-type transistors MP3 and MP4, word-line (WL), bit-line (BL), bit-line bar (BLB), storage nodes nO and nl, first floating-gate transistor 601 (e.g., p-type transistor MP5), second floating-gate transistor 602 (e.g., p-type transistor MP6), p-type supply transistors MP7 and MP8, coupled together as shown. While memory-bit cell 600 is shown having p-type access devices MP1 and MP2, these p-type access devices can be replaced with n-type access devices. In some embodiments, a store (RS) signal is used for causing floating-gate transistors 601 and 602 to restore states stored in storage nodes nO and nl . In some embodiments, p-type transistors MP7 and MP8 are powered by a first power supply Vddl . In some embodiments, transistors MP3 and MP5 are coupled to a second power supply Vdd2.

[0043] In some embodiments, during a restore operation (e.g., to restore logic states stored on storage nodes nO and nl), Vddl is powered up, Vdd2 is still at 0 V (e.g., it is discharged), RS is set to logic low (e.g., 0 V), BL and BLB are discharged to 0V, and word-line WL is set to Vddl level. In the restore operation, the state stored by the floating gate transistors 601 and 602 is copied to the SRAM cell storage nodes. For example, during a restore operation, power is restored to the SRAM and data is transferred from the floating-gate transistors 601 and 602 to the SRAM cell storage nodes nO and nl, respectively. Here, supply VddO is ramped on. The voltages on the SRAM cell restore to a known state as the currents through floating-gate transistors 601 and 602 are amplified to logic levels. For example, high current flows through floating-gate transistor 601 causing node nO to charge to VddO level, while low current flows through floating-gate transistor 602 causing node nl to remain at 0 V (e.g., discharged state).

[0044] In some embodiments, during a save operation, data is copied from the SRAM cell (e.g., copied from the storage nodes nO and nl of the SRAM cell) to the floating-gate transistors 601 and 602, respectively, and the power supply is gated (e.g., power supply is removed or reduced to 0V). The floating-gate write or save operation can happen without any data movement, in accordance with some embodiments. In some embodiments, the voltage differences between nO and nl in the SRAM cell apply a voltage across the gate oxide of floating-gate transistors 601 and 602, respectively, that write the cell. In this example, floating-gate transistor 601 saves a high state (e.g., writes a logic 1) while floating-gate transistor 602 saves a low state (e.g., writes a logic 0). For example, the control-gate voltage for floating-gate transistor 601 is Vdd while the control-gate voltage for floating-gate transistor 602 is Vss.

[0045] The write operation may be shortened by raising the SRAM supply voltage, in accordance with some embodiments. For example, at Vdd of 1.1 V, the required write time may be 10 μβ. However, because no data movement is required, all write operations can happen in parallel and so the total write time is may not be an issue, in accordance with some embodiments.

[0046] While the disclosure illustrates the use of floating-gate transistors for a static random access memory (SRAM), it can be used for any logic that is to store data. For example, floating-gate transistors can be used for register files, tristate driver, sequential circuits such as flip-flops and latches, and other circuits having cross-coupled inverters for storing data on a storage node.

[0047] Figs. 7A-B illustrate layout 700 and 720, respectively, of the memory-bit-cell with fully integrated floating-gate transistors, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 7A-B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Fig. 7A illustrates the node or net names of first floating-gate transistor 701/601, second floating-gate transistor 702/602, and SRAM bit-cell 703. Fig. 7B illustrates the transistor names of SRAM bit-cell 703.

[0048] While the length (and thus the foot-print) of the layout is larger than an SRAM bit-cell without floating-gate transistors, this layout is formed using the same layout design rules as a conventional SRAM cell. For example, no special layout design rules need to be developed for the process technology node for integrating floating-gate transistors into a memory cell. In one example, for efficient power gating, 12 KB of memory may be saved per processing core, and so the total area increase for such a memory with floating-gate transistors may be merely 1%.

[0049] Fig. 8 illustrates plot 800 showing gate leakage that provides write current, according to some embodiments. Here, x-axis is control-gate voltage (e.g., voltage on node 101), and y-axis is current per FinFET. Plot 800 shows that gate oxide leakage currents provide a charging current used for writing the floating-gate transistor 100 and leakage currents that limits retention. Plot 800 indicates the write current for high-Vt and low-Vt states of floating-gate transistor 100, and also indicates the retain current for high-Vt and low-Vt states of floating-gate transistor 100.

[0050] Fig. 9 illustrates plot 900 showing read current over retention time, according to some embodiments. Here, x-axis is time and y-axis is read current in μΑ/FinFET. Plot 900 shows that in this example, retention time is around 100 ms.

[0051] Fig 10 illustrates top view 1000 of a layout of floating-gate transistor 100, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0052] In some embodiments, an active region 1001 (e.g., n-diffusion or p-diffusion, depending on the type or transistor (p-type or n-type) and process technology) is defined according to the desired length and width of the floating-gate transistor 100. In some embodiments, source and drain regions are formed by known methods (e.g., doping regions on either sides of gate 1002).

[0053] In some embodiments, the source and drain regions are contacted via contact material 1003 and 1004, respectively. In this example, contact material 1003 forms the source region contact while contact material 1004 forms the drain region contact. A person skilled in the art would appreciate that source and drain regions may be identical regions, and the labels of "source" and "drain" are attributed according to the potentials applied to those regions.

[0054] In some embodiments, gate 1002 is any type of gate that the process technology node is using. For example, floating-gate transistor 100 may be a FinFET (Tri-gate transistor) or a regular planar transistor. The various embodiments for forming floating-gate transistor 100 is applicable to any type of transistor provided by the process technology node.

[0055] In some embodiments, gate 1002 is much wider than its length (e.g., W is greater than L). In some embodiments, source and drain contact material 1003 and 1004 do not extend along the entire width (W) of gate 1002. For example, source and drain contact material 1003 and 1004 are disposed within active region 1001 while gate 1002 may have a width that extends beyond active region 1001. In some embodiments, material used for source and drain contacts 1003 and 1004 is also used to form contact nodes 1005 and 1006. In some embodiments, contact material 1005 is deposited along gate 1002, without touching gate 1002, such that contact material 1005 extends along the width W of gate 1001 while leaving a gap or discontinuity 'D' between source contact material 1003 and contact material 1005. As such, no ohmic contact is made between contact material 1005 and gate 1002.

[0056] In some embodiments, contact material 1006 is deposited along gate 1002, without touching gate 1002, such that contact material 1006 extends along the width W of gate 1002 while leaving a gap or discontinuity 'D' between drain contact material 1004 and contact material 1006. As such, no ohmic contact is made between contact material 1 106 and gate 1002. In some embodiments, contact material 1005 is deposited along gate 1002, without touching gate 1002, such that contact material 1005 extends along the width W of gate 1002 while leaving a gap or discontinuity 'D' between source contact material 1003 and contact material 1005. As such, no ohmic contact is made between contact material 1005 and gate 1002.

[0057] In some embodiments, contact material 1003, 1004, 1005, and 1006 are deposited at the same time and formed of the same material. In some embodiments, contact material 1005 and 1006 are electrically coupled together to form capacitor around floating-gate 1002. In some embodiments, near or at the end of contact material 1005, a contact or via 1009 is formed. In some embodiments, near or at the end of contact material 1006, a contact or via 1010 is formed. In some embodiments, another metal layer 1009 is deposited over via/contact 1007 and 1008 such that contact material 1005 and 1006 is electrically coupled and wraps around gate 1002. In some embodiments, layer 1009 is a metal 0 (e.g., M0) layer. In some embodiments, layer 1009 is also formed of the same material as contact material used for 1003, 1004, 1005, and 1006. For example, the material includes one of: includes one of: Tungsten, Tantalum, Titanium, Copper, Nickel, or Aluminum, or a combination of them.

[0058] In some embodiments, gate 1002 may connect to gate contact material 1009.

In some embodiments, contact materials 1010 and 1011 may connect to gate contact material 1009. In some embodiments, control gate 1006 and 1005 may connect to vias 1007 and 1009 and metal layer 1012. In some embodiments, control gate conductors 1004, 1006, and 1012 may provide a capacitance to floating gate conductors 1010, 1011, 1009, and 1002.

[0059] Fig. 11 illustrates an alternate memory bit-cell 1100 with fully integrated floating-gate transistors for saving and restoring data to storage nodes during power-gating, according to some embodiments of the disclosure. In contrast to memory bit-cell 600, memory bit-cell 1100 connects the gate of transistor MP7 to node nl and connects or couples the gate of transistor MP8 to node nO. In this embodiment, no RS signal is used. During a restore operation, nodes nO and nl are discharged low so both transistors MP7 and MP8 are in a conductive mode. When supply Vddl turns on, nodes nO and nl will charge according to the states stored in gloating gate transistors 1101 and 1102.

[0060] Fig. 12 illustrates a smart device or a computer system or a SoC (System-on- Chip) with the floating-gate transistor, according to some embodiments. It is pointed out that those elements of Fig. 12 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0061] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors (BJT PNP/NPN), BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.

[0062] Fig. 12 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing

device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0063] In some embodiments, computing device 1600 includes first processor 1610 and network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant. Any of the various blocks of computing device 1600 can have the floating-gate transistor(s) of various embodiments.

[0064] In some embodiments, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors,

microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0065] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0066] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user. [0067] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0068] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0069] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0070] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600. In some embodiments, Memory subsystem 1660 includes the scheme of analog in-memory pattern matching with the use of resistive memory elements. In

some embodiments, memory subsystem includes the floating-gate transistor, according to some embodiments.

[0071] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0072] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0073] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0074] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to

connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0075] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0076] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0077] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0078] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0079] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for

simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0080] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0081] Example 1 is an apparatus which comprises: a gate disposed between a source and a drain, the gate having a length and a width, wherein the width is orthogonal to the length, wherein the length extends between the source and drain, and wherein the width extends away from the source and drain, wherein the width is greater than the length; a first conductor extending along the width of the gate; a second conductor extending along the width of the gate such that the first and second conductors are parallel to one another, and wherein the first and second conductors are disposed on either sides of the gate; a third conductor coupled to the source; a fourth conductor coupled to the drain; and wherein the first and second conductors are disconnected from the third and fourth conductors.

[0082] Example 2 includes all features of claim 1 , wherein the first and second conductors are coupled together.

[0083] Example 3 is according to any one of examples 1 to 2, wherein the first, second, third, and fourth conductors comprise a same material.

[0084] Example 4 includes all features of example 3, wherein the material for the first, second, third, and fourth conductors includes one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

[0085] Example 5 includes all features of example 1 , wherein the fourth conductor is coupled to a storage node of a memory cell.

[0086] Example 6 is according to any one of examples 1 to 3, wherein the third conductor is coupled to a transistor.

[0087] Example 7 includes all features of example 6, wherein the transistor is coupled to a power supply node.

[0088] Example 8 includes all fetures of example 6, wherein the transistor is controllable by a control signal.

[0089] Example 9 is an apparatus which comprises: a first transistor coupled to a power supply node; a memory cell; and a second transistor coupled to the memory cell and the first transistor, wherein the second transistor comprises a gate which is independent of an ohmic contact and is controlled by charging or discharging a conductor which is at least partially around the gate.

[0090] Example 10 includes all features of example 9, wherein the second transistor is coupled to a storage node of the memory cell.

[0091] Example 11 is according to any one of examples 9 to 10, wherein the second transistor includes source and drain regions coupled to first and second conductors, respectively, wherein the first and second conductors comprise a material which is same as a material of the conductor which is at least partially around the gate of the second transistor.

[0092] Example 12 includes all features of example 1 1, wherein the material includes one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

[0093] Example 13 includes all features of example 9, wherein the memory cell is an

SRAM memory bit-cell.

[0094] Example 14 includes all features of example 9, wherein the memory cell is part of a data flip-lop (DFF).

[0095] Example 15 is a method which comprises: disposing a gate between a source and a drain, the gate having a length and a width, wherein the length is orthogonal to the width, wherein the length extends between the source and drain, and wherein the width extends away from the source and drain, wherein the width is greater than the length; forming a first conductor extending along the width of the gate;forming a second conductor extending along the width of the gate such that the first and second conductors are parallel to one another, and wherein the first and second conductors are disposed on either sides of the gate; forming a third conductor coupled to the source; and forming a fourth conductor coupled to the drain, wherein the first, second, third, and fourth conductors comprise a same material.

[0096] Example 16 includes all features of example 15, wherein the first and second conductors are disconnected from the third and fourth conductors.

[0097] Example 17 includes all features of example 15, and comprises coupling the first and second conductors together.

[0098] Example 18 includes all fearures of example 15, wherein the material for the first, second, third, and fourth conductors include one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

[0099] Example 19 includes all features of example 15, and comprises coupling the fourth conductor to a storage node of a memory cell.

[00100] Example 20 is according to any one of examples 15 to 19 comprises coupling the third conductor to a transistor.

[00101] Example 21 includes all features of example 20, and comprises coupling the transistor to a power supply node.

[00102] Example 22 is according to any one of claims 20 to 21 comprises controlling the transistor by a control signal.

[00103] Example 23 is a sytem which comprises: a processor; a memory coupled to the processor, wherein the memory include an apparatus according to any one of examples 1 to 8, or any one of examples 9 to 14; and a wireless interface to allow the processor to

communicate with another device.

[00104] Example 24 is a method which comprises: forming a first transistor coupled to a power supply node; forming a memory bit-cell; and forming a second transistor coupled to the memory bit-cell and the first transistor, wherein the second transistor comprises a gate which is independent of an ohmic contact and is controlled by charging or discharging a conductor which is at least partially around the gate.

[00105] Example 25 includes all features of example 24, and comprises: coupling the second transistor to a storage node of the memory bit-cell.

[00106] Example 26 is according to any one of examples 24 to 25, comprises coupling source and drain regions of the second transistor coupled to first and second conductors, respectively, wherein the first and second conductors comprise a material which is same as a material of the conductor which is at least partially around the gate of the second transistor.

[00107] Example 27 includes all features of example 26, wherein the material includes one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

[00108] Example 28 is an apparatus which comprises: a memory cell; and a transistor coupled to the memory cell, wherein the transistor comprises a gate which is independent of an ohmic contact and is controlled by charging or discharging a conductor which is at least partially around the gate.

[00109] Example 29 includes all features of example 28, wherein the transistor is coupled to a storage node of the memory cell.

[00110] Example 30 is according to any one of examples 28 to 29, wherein the transistor includes source and drain regions coupled to first and second conductors, respectively, wherein the first and second conductors comprise a material which is same as a material of the conductor which is at least partially around the gate of the transistor.

[00111] Example 31 includes all features of example 30, wherein the material includes one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

[00112] Example 32 includes all features of example 28, wherein the memory cell is an

SRAM memory bit-cell.

[00113] Example 33 includes all features of example 28, wherein the memory cell is part of a data flip-lop (DFF).

[00114] Example 34 is an apparatus comprises: a gate disposed between source and drain regions, the gate having a length and a width, wherein the width is orthogonal to the length, wherein the length extends between the source and drain regions, and wherein the width extends away from the source and drain regions, wherein the width is greater than the length; a first conductor extending along the width of the gate; a second conductor coupled to the source region; and a third conductor coupled to the drain region; wherein the first is disconnected from the second or third conductors.

[00115] Example 35 includes all features of example 34, and comprises a fourth conductor extending along the width of the gate such that the first and fourth conductors are parallel to one another, and wherein the first and fourth conductors are disposed on either sides of the gate.

[00116] Example 36 includes all features of example 35, wherein the first and fourth conductors are coupled together.

[00117] Example 37 is according to any one of examples 35 to 36, wherein the first, second, third, and fourth conductors comprise a same material.

[00118] Example 38 includes all features of example 35, wherein the material for the first, second, third, and fourth conductors include one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

[00119] Example 39 includes all features of example 34, wherein the third conductor is coupled to a storage node of a memory cell.

[00120] Example 40 is according to any one of examples 34 to 37, wherein the second conductor is coupled to a transistor.

[00121] Example 41 includes all features of example 40, wherein the transistor is coupled to a power supply node.

[00122] Example 42 includes all features of example 40, wherein the transistor is controllable by a control signal.

[00123] Example 43 is a method which comprises: forming a memory cell; forming a transistor; and coupling thet transistor to the memory cell, wherein the transistor comprises a gate which is independent of an ohmic contact and is controlled by charging or discharging a conductor which is at least partially around the gate.

[00124] Example 44 includes all features of example 43, and comprises coupling the transistor to a storage node of the memory cell.

[00125] Example 45 is according to any one of examples 43 to 44, wherein the transistor includes source and drain regions coupled to first and second conductors, respectively, wherein the first and second conductors comprise a material which is same as a material of the conductor which is at least partially around the gate of the transistor.

[00126] Example 46 includes all features of example 45, wherein the material includes one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

[00127] Example 47 includes all features of example 43, wherein the memory cell is an

SRAM memory bit-cell.

[00128] Example 48 includes all features of example 43, wherein the memory cell is part of a data flip-lop (DFF).

[00129] Example 49 is a method whih comprises: forming a gate disposed between source and drain regions, the gate having a length and a width, wherein the width is orthogonal to the length, wherein the length extends between the source and drain regions, and wherein the width extends away from the source and drain regions, wherein the width is greater than the length; forming a first conductor extending along the width of the gate; forming a second conductor coupled to the source region; and forming a third conductor coupled to the drain region; wherein the first is disconnected from the second or third conductors.

[00130] Example 50 includes all features of example 49, and comprises forming a fourth conductor extending along the width of the gate such that the first and fourth conductors are parallel to one another, and wherein the first and fourth conductors are disposed on either sides of the gate.

[00131] Example 51 includes all features of example 50, and comprises coupling the first and fourth conductors together.

[00132] Example 52 is according to any one of examples 50 to 51, wherein the first, second, third, and fourth conductors comprise a same material.

[00133] Example 53 includes all features of example 50, wherein the material for the first, second, third, and fourth conductors include one of: Tungsten, Tantalum, Titanium, Nickel, or Aluminum.

[00134] Example 54 includes all features of example 49, wherein the third conductor is coupled to a storage node of a memory cell.

[00135] Example 55 is according to any one of examples 49 to 54 comprises coupling the second conductor to a transistor.

[00136] Example 56 includes all features of example 55, and comprises coupling the transistor to a power supply node.

[00137] Example 57 is according to any one of examples 55 or 56 comprises controlling the transistor by a control signal.

[00138] Example 58 is a system comprises: a processor; a memory coupled to the processor, wherein the memory include an apparatus according to any one of examples 28 to 33, or any one of examples 34 to 42; and a wireless interface to allow the processor to communicate with another device.

[00139] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.