البحث في مجموعات البراءات الوطنية والدولية

1. (WO2018186197) SOLID STATE IMAGING DEVICE AND ELECTRONIC APPARATUS

Pub. No.:    WO/2018/186197    International Application No.:    PCT/JP2018/011570
Publication Date: Fri Oct 12 01:59:59 CEST 2018 International Filing Date: Sat Mar 24 00:59:59 CET 2018
IPC: H01L 27/146
H01L 21/02
H01L 21/3205
H01L 21/768
H01L 23/522
H01L 25/065
H01L 25/07
H01L 25/18
H04N 5/369
Applicants: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
ソニーセミコンダクタソリューションズ株式会社
Inventors: KAMESHIMA, Takatoshi
亀嶋 隆季
HASHIGUCHI, Hideto
橋口 日出登
MITSUHASHI, Ikue
三橋 生枝
HORIKOSHI, Hiroshi
堀越 浩
SHOHJI, Reijiroh
庄子 礼二郎
ISHIDA, Minoru
石田 実
IIJIMA, Tadashi
飯島 匡
HANEDA, Masaki
羽根田 雅希
Title: SOLID STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
Abstract:
[Problem] To improve the performance of a solid state imaging device. [Solution] A solid state imaging device that is formed by laminating, in order, a first substrate, a second substrate, and a third substrate. The first substrate has: a first semiconductor substrate that has formed thereon a pixel unit that comprises an array of pixels; and a first multilayer wiring layer that is laminated upon the first semiconductor substrate. The second substrate has: a second semiconductor substrate that has formed thereon a circuit that has a prescribed function; and a second multilayer wiring layer that is laminated upon the second semiconductor substrate. The third substrate has: a third semiconductor substrate that has formed thereon a circuit that has a prescribed function; and a third multilayer wiring layer that is laminated upon the third semiconductor substrate. The first substrate and the second substrate are adhered to each other such that the first multilayer wiring layer and the second multilayer wiring layer face. A first connection structure that is for electrically connecting two of the first substrate, the second substrate, and the third substrate includes a via that is structured such that a conductive material is embedded in or formed as a film on inner walls of: a first through hole that exposes first wiring that is included in one of the first multilayer wiring layer, the second multilayer wiring layer, and the third multilayer wiring layer; and another through hole that exposes second wiring that is included in a multilayer wiring layer that is among the first multilayer wiring layer, the second multilayer wiring layer, and the third multilayer wiring layer and does not include the first wiring.