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1. (WO2018125120) TECHNIQUES FOR FORMING DUAL-STRAIN FINS FOR CO-INTEGRATED N-MOS AND P-MOS DEVICES
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CLAIMS

What is claimed is:

1. An integrated circuit (IC) comprising:

a substrate;

a first transistor above the substrate and including

a first gate,

a first channel region below the first gate and including tensile- strained semiconductor material, and

first source and drain (S/D) regions adjacent the first channel region and including n-type doped semiconductor material; and

a second transistor above the substrate and including

a second gate,

a second channel region below the second gate and including compressive- strained semiconductor material, and

second source and drain (S/D) regions adjacent the second channel region and including p-type doped semiconductor material.

2. The IC of claim 1, wherein the compressive-strained semiconductor material includes at least 40 percent more germanium (Ge) content by atomic percentage than the tensile-strained semiconductor material.

3. The IC of claim 1, wherein the wherein the compressive-strained semiconductor material includes at least 60 percent more germanium (Ge) content by atomic percentage than the tensile- strained semiconductor material.

4. The IC of claim 1, wherein the tensile-strained semiconductor material includes silicon (Si).

5. The IC of claim 1, wherein the tensile-strained semiconductor material includes silicon germanium (SiGe).

6. The IC of claim 1, wherein the compressive-strained semiconductor material includes silicon germanium (SiGe).

7. The IC of claim 1, wherein the compressive-strained semiconductor material includes germanium (Ge).

8. The IC of claim 1, wherein the compressive-strained semiconductor material includes at least 0.5 gigapascals (GPa) of compressive stress.

9. The IC of claim 1, wherein the tensile- strained semiconductor material includes at least 0.5 gigapascals (GPa) of tensile stress.

10. The IC of claim 1, further comprising an intervening layer between the substrate and the first transistor, the intervening layer also between the substrate and the second transistor, wherein the intervening layer includes silicon germanium (SiGe).

11. The IC of claim 10, wherein at least a portion of the SiGe included in the intervening layer is relaxed and thereby includes no stress.

12. The IC of claim 10, wherein the SiGe included in the intervening layer includes a germanium (Ge) concentration in the range of 20-80 percent.

13. The IC of claim 10, wherein the intervening layer includes a thickness between the substrate and the first transistor of at least 20 nanometers (nm).

14. The IC of claim 1, wherein at least one of the first and second channel regions includes a finned configuration.

15. The IC of claim 1, wherein at least one of the first and second channel regions includes a nanowire configuration.

16. The IC of claim 1, further comprising a complementary metal-oxide-semiconductor (CMOS) circuit including the first and second transistors.

17. A computing system comprising the IC of any of claims 1 -16.

18. An integrated circuit (IC) comprising:

a substrate;

a first transistor above the substrate and including

a first gate,

a first channel region below the first gate and including tensile-strained semiconductor material, and

first source and drain (S/D) regions adjacent the first channel region; and a second transistor above the substrate and including

a second gate,

a second channel region below the second gate and including compressive- strained semiconductor material, and

second source and drain (S/D) regions adjacent the second channel region;

wherein the compressive-strained semiconductor material includes at least 40 percent more germanium (Ge) content by atomic percentage than the tensile-strained semiconductor material.

19. The IC of claim 18, wherein the first transistor is an n-channel metal-oxide-semiconductor field-effect transistor (n-MOS) device and wherein the second transistor is a p-channel metal-oxide-semiconductor field-effect transistor (p-MOS) device.

20. The IC of claim 18, wherein the wherein the compressive-strained semiconductor material includes at least 60 percent more germanium (Ge) content by atomic percentage than the tensile- strained semiconductor material.

21. The IC of any of claims 18-20, further comprising an intervening layer between the substrate and the first transistor, the intervening layer also between the substrate and the second transistor, wherein the intervening layer includes silicon germanium (SiGe).

22. A method of forming an integrated circuit (IC), the method comprising:

providing a substrate;

forming a first transistor above the substrate, the first transistor including a first gate, a first channel region below the first gate and including tensile-strained semiconductor material, and first source and drain (S/D) regions adjacent the first channel region and including n-type doped semiconductor material; and forming a second transistor above the substrate, the second transistor including a second gate, a second channel region below the second gate and including compressive- strained semiconductor material, and second S/D regions adjacent the second channel region and including p-type doped semiconductor material.

23. The method of claim 22, wherein at least one of the first and second channel regions is formed using a replacement fin scheme that includes removing original fins to form fin- shaped trenches and forming the at least one of the first and second channel regions in the fin-shaped trenches.

24. The method of claim 22, wherein at least one of the first and second channel regions is formed from a blanket-grown layer.

25. The method of any of claims 22-24, further comprising forming a silicon germanium (SiGe) buffer layer prior to forming the first and second transistors, wherein the SiGe buffer layer is between the substrate and the first transistor and wherein the SiGe buffer layer is also between the substrate and the second transistor.