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1. (WO2018106233) INTEGRATED CIRCUIT DEVICE WITH CRENELLATED METAL TRACE LAYOUT
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CLAIMS

What is claimed is:

1. An integrated circuit (IC) cell having a crenellated trace layout, wherein:

the crenellated trace layout include a plurality of traces extending in a direction;

individual traces of the plurality intersect only one boundary of the cell; and

adjacent ones of the plurality are staggered to intersect boundaries on opposite sides of the cell.

2. The IC cell of claim 1, wherein individual traces of the plurality are within a first interconnect level, and have an end that is laterally offset from that of an adjacent trace by at least a width of an orthogonal trace within a second interconnect level.

3. The IC cell of claim 2, wherein the end of individual traces of the plurality is laterally offset from that of an adjacent trace by approximately the width of an orthogonal trace in the second interconnect level summed with half the distance separating the orthogonal trace from an adjacent trace in the second interconnect level.

4. The IC cell of claim 2, further comprising a conductive via coupling the orthogonal trace to at least one of the crenellated traces.

5. The IC cell of claim 4, wherein:

the orthogonal trace is coupled to a transistor drain; and

the via is separated from the end of a crenellated trace by approximately half the distance separating the orthogonal trace from an adjacent trace in the second interconnect level.

6. The IC cell of claim 5, further comprising:

a plurality of gate electrodes extending in the first direction and each coupled to a

transistor channel; and

a back-side interconnect trace coupled to a transistor source terminal, the back-side interconnect trace disposed over a side of the transistor channel opposite that of a gate electrode.

7. An integrated IC block, comprising:

a first IC cell comprising the IC cell of claim 1; and

a second IC cell sharing one boundary with the first IC cell, wherein:

the second IC cell has a second crenellated trace layout comprising a second plurality of traces extending in the direction, traces of the second plurality intersecting only one boundary of the second IC cell, and having second ends that are laterally offset from each other in the direction by at least the width of an orthogonal trace in a second interconnect level; and

wherein a trace of the plurality intersecting the shared boundary is laterally offset in the direction from a trace of the second plurality by at least the width of an orthogonal trace in the second interconnect level.

8. The IC block of claim 7, wherein:

the crenellated trace layout has a crenellation phase complementary to a second

crenellation phase of the second crenellated layout;

individual traces of the first cell that are not laterally offset from a trace of the second cell by at least the width of an orthogonal trace in the second interconnect level have continuity with the trace of the second cell.

9. The IC block of claim 7, wherein:

the crenellated trace layouts of the first and second cells have the same crenellation

phase; and

individual traces of the plurality are aligned in the second direction with individual traces of the second plurality, and no traces of the plurality that intersect the shared boundary has continuity with any traces of the second plurality that intersect the shared boundary.

10. The IC block of claim 7, wherein:

the crenellated trace layouts of the first and second cells have the same crenellation

phase;

a subset of the plurality of traces are aligned in a second direction, orthogonal to the first direction, with a subset of the second plurality of traces; and

the traces aligned in the second direction that also intersect the shared boundary have continuity across the shared boundary.

11. An integrated circuit (IC) cell, comprising:

a transistor gate electrode trace extending in a first direction over a transistor channel; a first interconnect level comprising at least a first interconnect trace adjacent to a second interconnect trace and extending in a second direction over the gate electrode trace, wherein the first and second interconnect traces have a first trace width and are separated from one another by an interconnect trace spacing; and

a second interconnect level comprising at least a third interconnect trace adjacent to a fourth interconnect trace and extending in the first direction, wherein:

the third interconnect trace extends over the first interconnect trace and has a trace end located over the first interconnect trace spacing adjacent to the first interconnect trace; and

the fourth interconnect traces extends over the second interconnect trace, but not over the first interconnect trace, and has an end laterally offset in the first direction from that of the third interconnect trace by a distance at least equal to the first trace width.

12. The IC cell of claim 11, wherein:

the trace end of the third interconnect trace is laterally offset from an edge of the first interconnect trace by approximately half the interconnect trace spacing; and the trace end of the fourth interconnect trace is laterally offset in the first direction from that of the third interconnect trace by approximately the first trace width summed with half the interconnect trace spacing.

13. The IC cell of claim 11, wherein:

the first interconnect level further comprises:

a fifth interconnect trace extending in the second direction over the gate electrode trace and adjacent to the second interconnect trace; and

a sixth interconnect trace extending in the second direction over the gate electrode trace and adjacent to the fifth interconnect trace; and

the third and fourth interconnect traces extend over at least one of the fifth and sixth interconnect traces.

14. The IC cell of claim 13, wherein:

the third interconnect trace extends over the fifth interconnect trace and has a second trace end located over the interconnect trace spacing between the fifth and sixth interconnect traces; and

the fourth interconnect trace extends over the fifth and sixth interconnect traces and has a second trace end laterally offset in the first direction from an end of the third interconnect trace by at least the first trace width.

15. The IC cell of claim 14, wherein the third and fourth traces have the same length in the first direction.

16. The IC cell of claim 13, wherein:

the second interconnect level further comprises:

a seventh interconnect trace extending in the first direction and adjacent to the fourth interconnect trace; and

an eighth interconnect trace extending in the first direction and adjacent to the seventh interconnect trace;

the seventh interconnect trace extends over the first interconnect trace and has a trace end located over the interconnect trace spacing adjacent to the first interconnect trace; and

the eighth interconnect traces extends over the second interconnect trace, but not the first interconnect trace, and has a trace end laterally offset from that of the seventh interconnect trace by a distance in the first direction that is at least equal to the first trace width.

17. The IC cell of claim 16, wherein:

the seventh interconnect trace extends over the fifth interconnect trace and has a second trace end located over the interconnect trace spacing between the fifth and sixth interconnect traces; and

the eighth interconnect trace extends over the fifth and sixth interconnect traces and has a second trace end laterally offset from that of the third interconnect trace in the first direction by a distance that is at least equal to the first trace width.

18. The IC cell of claim 16, wherein:

the trace ends of the first and seventh interconnect traces are aligned with each other; the trace ends of the second and eighth interconnect traces are aligned with each other; the second trace ends of the first and seventh interconnect traces are aligned with each other; and

the second trace ends of the second and eighth interconnect traces are aligned with each other.

19. The IC cell of claim 11, further comprising a second gate electrode trace extending in the first direction over a second transistor channel and adjacent to the gate electrode, wherein:

the gate electrode trace is located between the third and fourth interconnect traces; and

the second gate electrode trace is located between the seventh and eighth

interconnect traces.

20. The IC cell of claim 11, further comprising a via interconnecting at least one of the first, second, fourth or fifth interconnect traces to at least one of the third, fourth, fifth, or sixth interconnect traces.

21. The IC cell of claim 11, further comprising a back-side interconnect trace coupled to a transistor source terminal; and

wherein at least one of the first, second, fourth or fifth interconnect traces is coupled to a transistor drain terminal.

22. A method of fabricating an integrated circuit (IC) cell, the method comprising:

forming a gate electrode extending in a first direction over a transistor channel

semiconductor;

forming a first interconnect level comprising at least a first interconnect trace adjacent to a second interconnect trace and extending in a second direction over the gate electrode, wherein the first and second interconnect traces have a first trace width and are separated from one another in the first direction by an interconnect trace spacing;

forming a second interconnect level over the first interconnect level, the second

interconnect level comprising a plurality of crenellated traces extending in the first direction, wherein:

individual traces of the plurality intersect only one boundary of the cell;

adjacent traces of the plurality are staggered in the first direction to intersect boundaries on opposite sides of the cell; and

individual traces of the plurality have an end that is laterally offset from that of an adjacent trace by a distance in the first direction that is at least equal to the first trace width.

23. The method of claim 22, wherein forming the second interconnect level further

comprises forming at least a third interconnect trace adjacent to a fourth interconnect trace and extending in the first direction, wherein:

the third interconnect trace extends over the first interconnect trace and has a trace end located over the interconnect trace spacing adjacent to the first interconnect trace; and

the fourth interconnect traces extends over the second interconnect trace, but not the first interconnect trace, and has a trace end laterally offset from that of the third interconnect trace by a distance in the first direction that is at least equal to the first trace width.