البحث في مجموعات البراءات الوطنية والدولية

1. (WO2016135500) ERROR DETECTION CIRCUITRY FOR USE WITH MEMORY

Pub. No.:    WO/2016/135500    International Application No.:    PCT/GB2016/050500
Publication Date: Fri Sep 02 01:59:59 CEST 2016 International Filing Date: Sat Feb 27 00:59:59 CET 2016
IPC: G06F 11/10
Applicants: ARM LTD
Inventors: CHEN, Andy Wangkun
BHARGAVA, Mudit
MEYER, Paul
CHANDRA, Vikas
Title: ERROR DETECTION CIRCUITRY FOR USE WITH MEMORY
Abstract:
Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.