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الإعدادات

الإعدادات

1. US08576625 - Decoder parameter estimation using multiple memory reads

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Claims

1. An apparatus, comprising:
a memory array; and
control circuitry coupled to the memory array, wherein the control circuitry is configured to
based at least on a plurality of read comparison results, determine a number of memory cells of the memory array that have threshold voltages that fall into each of a plurality of voltage ranges, wherein (i) N1 represents a number of memory cells of the memory array that have threshold voltages that fall into a first voltage range of the plurality of voltage ranges, (ii) N2 represents a number of memory cells of the memory array that have threshold voltages that fall into a second voltage range of the plurality of voltage ranges, and (iii) N represents a total number of memory cells of the memory array on which the plurality of read comparison results are based,
determine (i) a first factor p1 that is based on a ratio of N1 and N, and (ii) a second factor p2 that is based on a ratio of N2 and N,
based at least on (i) the number of memory cells that have threshold voltages in each of the plurality of voltage ranges and (ii) the first factor p1 and the second factor p2, estimate an offset amount that a center voltage between two threshold voltage distributions differs from a center reference voltage, and
read one or more of the plurality of memory cells based at least in part on the estimated offset amount.
2. The apparatus of claim 1,
wherein the center reference voltage is an original center reference voltage,
wherein the control circuitry is further configured to determine a modified center reference voltage based at least in part on the original center reference voltage and the offset amount, and
wherein the control circuitry is further configured to read one or more of the plurality of memory cells based at least in part on the modified center reference voltage.
3. The apparatus of claim 1, wherein
the control circuitry is further configured to perform an initial read based on the center reference voltage, and
the control circuitry is further configured to perform, upon a determination of a decode failure associated with the initial read, the reads of one or more of the plurality of memory cells of the memory array using a plurality of read reference voltages.
4. The apparatus of claim 1, wherein each of the plurality of ranges have at least one end-point between a mean of the two threshold voltages distributions.
5. The apparatus of claim 3, wherein each of the plurality of read reference voltages are between two threshold voltage distributions.
6. The apparatus of claim 1, wherein the control circuitry is further configured to read one or more of the plurality of memory cells based at least in part on information derived from the estimated offset amount, wherein said information includes updated log likelihood ratios for each of the plurality of voltage ranges.
7. The apparatus of claim 1, wherein the control circuitry is further configured to read one or more of the plurality of memory cells based at least in part on information derived from the estimated offset amount, wherein said information includes a new read reference voltage determined using the estimated offset amount.
8. The apparatus of claim 1, wherein
the control circuitry is further configured to estimate the offset amount in part by iterative calculation of sets of bin data to determine a threshold voltage distribution parameter set that approximates the determined numbers of memory cells that have threshold voltages in each of the plurality of voltage ranges, and
the parameter set includes estimated offset amounts of the two threshold voltage distributions and variance estimates of the two threshold voltage distributions.
9. The apparatus of claim 1, wherein the control circuitry is further configured to estimate the offset amount by use of a bisection method that iteratively solves the following equations upon a determination of starting points for f(x) and g(σ):
where x is offset, where σ is square-root of variance, where r 1, r 2, and r 3 are the plurality of read reference voltages, and where:
10. The apparatus of claim 1, wherein the control circuitry is further configured to estimate the offset amount by iteration of the following equations a fixed number of times to converge on a value for x:

(NB)

           x=1−(σ* Q −1(2 p 2)+ r 3)
where x is offset, where σ is variance, where r 1, r 2, and r 3 are the plurality of read reference voltages, and where:
11. A method, comprising:
based at least on a plurality of read comparison results, determining a number of memory cells that have threshold voltages that fall into each of a plurality of voltage ranges, wherein (i) N1 represents a number of memory cells that have threshold voltages that fall into a first voltage range of the plurality of voltage ranges, (ii) N2 represents a number of memory cells of the memory array that have threshold voltages that fall into a second voltage range of the plurality of voltage ranges, and (iii) N represents a total number of memory cells of the memory array on which the plurality of read comparison results are based;
determining (i) a first factor p1 that is based on a ratio of N1 and N, and (ii) a second factor p2 that is based on a ratio of N2 and N;
based at least on (i) the numbers of memory cells that have threshold voltages in each of the plurality of voltage ranges and (ii) the first factor p1 and the second factor p2, estimating an offset amount that a center voltage between two threshold voltage distributions differs from a center reference voltage used to read the plurality of memory cells;
deriving information from the estimated offset amount; and
reading one or more of the plurality of memory cells using the information derived from the estimated offset amount.
12. The method of claim 11, further comprising:
performing an initial read based on the center reference voltage,
wherein said determining the number of memory cells and said estimating the offset amount occur upon a determination of a decode failure associated with the initial read.
13. The method of claim 11, wherein the information derived from the estimated offset amount includes updated log likelihood ratios for one or more of the plurality of voltage ranges.
14. The method of claim 11, wherein the information derived from the estimated offset amount includes a new read reference voltage determined using the offset amount.
15. The method of claim 11, wherein
the estimating the offset amount includes iterative calculation of sets of bin data to determine a distribution parameter set that approximates the determined numbers of memory cells that have threshold voltages in each of the plurality of voltage ranges, and
the distribution parameter set includes the offset estimates of the two threshold voltage distributions and variance estimates of the two threshold voltage distributions.
16. A system comprising:
a memory device including a memory array;
a memory controller coupled to the memory device and configured to
receive from the memory device a plurality of comparison results resulting from a plurality of reads on a plurality of memory cells of the memory array using a plurality of read reference voltages, including a center reference voltage,
based at least on the plurality of comparison results, determine a number of memory cells of the memory array that have threshold voltages that fall into each of a plurality of voltage ranges, wherein (i) N1 represent a number of memory cells of the memory array that have threshold voltages that fall into a first voltage range of the plurality of voltage ranges, (ii) N2 represent a number of memory cells of the memory array that have threshold voltages that fall into a second voltage range of the plurality of voltage ranges, and (iii) N represent a total number of memory cells of the memory array on which the plurality of read comparison results are based,
determine (i) a first factor p1 that is based on a ratio of N1 and N, and (ii) a second factor p2 that is based on a ratio of N2 and N,
based at least on the numbers of memory cells that have threshold voltages in each of the plurality of voltage ranges, estimate an offset amount that a center voltage between two distributions of the threshold voltages differs from the center reference voltage;
derive information from the estimated offset amount, and
cause the memory device to read one or more of the plurality of memory cells using information derived from the estimated offset amount.
17. The system of claim 16, wherein the information derived from the estimated offset amount includes updated log likelihood ratios for each of the plurality of voltage ranges.
18. The system of claim 16, wherein the information derived from the estimated offset amount includes a new read reference voltage determined using the estimated offset amount.
19. The system of claim 16, wherein the memory controller is configured to estimate the offset amount by use of a bisection approach that iteratively solves the following equations using determined starting points for f(x) and g(σ):
where x is offset, where σ is variance, where r 1, r 2, and r 3 are the plurality of read reference voltages, and where:
20. The system of claim 16, wherein the memory controller is configured to estimate the offset amount by iteration of the following equations a fixed number of times to converge on a value for x:

(NB)

           x=1−(σ* Q −1(2 p 2)+ r 3)
where x is offset, where σ is variance, where r 1, r 2, and r 3 are the plurality of read reference voltages, and where: