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1. (US20160018446) Gate drive under-voltage detection
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Claims

1. An inverter comprising:
a phase switch having an insulated gate;
a complementary transistor pair adapted to receive a supply voltage and a PWM signal to alternately charge and discharge the insulated gate;
a comparator comparing a voltage at the insulated gate with a reference voltage representing a gate drive fault to generate a first logic signal;
a latch sampling the first logic signal when the PWM signal has a value corresponding to charging the insulated gate;
a logic circuit inhibiting charging of the insulated gate when the latched logic signal indicates the gate drive fault; and
a second comparator for comparing a voltage across the phase switch to a second reference voltage indicative of an On state of the phase switch, wherein the latch is triggered by the second comparator when the on state is detected.
2. The inverter of claim 1 wherein the gate drive fault is an under-voltage fault of the supply voltage.
3. The inverter of claim 2 wherein the reference voltage is configured to indicate the under-voltage fault whenever the supply voltage is less than 90% of a target value.
4. The inverter of claim 1 wherein the gate drive fault includes an insulation fault of the insulated gate and a conduction fault of the complementary transistor pair.
5. The inverter of claim 1 wherein the latch is triggered by a falling edge of the PWM signal.
6. The inverter of claim 1 wherein the latch is comprised of a D-type flip-flop.
7. A method of detecting a gate drive fault of an insulated gate phase switch in an inverter of an electrified vehicle, comprising:
coupling a PWM signal to a complementary transistor pair to alternately charge and discharge the insulated gate of the phase switch during charge and discharge phases of the PWM signal, respectively;
comparing a voltage at the insulated gate to a reference voltage representing a gate drive fault to generate a first logic signal;
latching the first logic signal once during the charge phase of the PWM signal;
inhibiting the charging of the insulated gate after the latched logic signal indicates the gate drive fault; and
comparing a voltage across the phase switch to a second reference voltage indicative of an on state of the phase switch, wherein the latching step is triggered by the second comparator when the on state is detected.
8. The method of claim 7 wherein the gate drive fault is an under-voltage fault of the supply voltage, and wherein the reference voltage is configured to indicate the under-voltage fault whenever the supply voltage is less than 90% of a target value.
9. The method of claim 7 wherein the gate drive fault includes an insulation fault of the insulated gate and a conduction fault of the complementary transistor pair.
10. The method of claim 7 wherein the latching step is triggered by a falling edge of the PWM signal.