OMPI – Pesquisa nas coleções internacionais e nacionais de patentes

1.WO/1993/001545HIGH-PERFORMANCE RISC MICROPROCESSOR ARCHITECTURE

WO - 21.01.1993

CIP G06F 9/30 № do pedido PCT/JP1992/000868 Requerente SEIKO EPSON CORPORATION Inventor NGUYEN, Le Trong

The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths allowing for the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream. The target conditional branch prefetch path allows both possible instruction streams for a conditional branch instruction to be prefetched. The procedural instruction prefetch path allows a supplementary instruction stream to be accessed without clearing the main or target prefetch buffers. Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer. An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file by the functional units as necessary for the execution of the respective instructions.

2.WO/2011/004755SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

WO - 13.01.2011

CIP H01L 21/336 № do pedido PCT/JP2010/061221 Requerente SEMICONDUCTOR ENERGY LABORATORY CO., LTD. Inventor YAMAZAKI, Shunpei

It is an object to manufacture and provide a highly reliable display device including a thin film transistor with a high aperture ratio which has stable electric characteristics. In a manufacturing method of a semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is formed using an oxide semiconductor film, a heat treatment for reducing moisture and the like which are impurities and for improving the purity of the oxide semiconductor film (a heat treatment for dehydration or dehydrogenation) is performed. Further, an aperture ratio is improved by forming a gate electrode layer, a source electrode layer, and a drain electrode layer using conductive films having light transmitting properties.

3.WO/1996/024138NONVOLATILE MEMORY DEVICE AND REFRESHING METHOD

WO - 08.08.1996

CIP G11C 11/56 № do pedido PCT/JP1995/002260 Requerente HITACHI, LTD. Inventor MIWA, Hitoshi

In a write operation, data of a plurality of bits is converted to data (multi-value data) corresponding to the combinations of bits by a logic circuit, and the converted data are sequentially transferred to a latch circuit connected to bit lines of a memory array. Write pulses are generated in accordance with the data held by the latch circuit and then applied to a memory device in a select state so as to impart a threshold value corresponding to the multi-value data to the memory device. In a read operation, the read voltage is changed to an intermediate value of the respective threshold voltages so as to read out the state of the memory device. The read voltage is then transferred to a register storing the multi-value data and held by it. The original bit data is restored by an inverse conversion logic circuit on the basis of the multi-value data stored in this register. Therefore, the peripheral circuits of the memory array can be kept at a relatively small scale, and the write operation can be accomplished within a short time.

4.WO/2011/058866SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

WO - 19.05.2011

CIP H01L 29/786 № do pedido PCT/JP2010/068795 Requerente SEMICONDUCTOR ENERGY LABORATORY CO., LTD. Inventor YAMAZAKI, Shunpei

An object is to provide a semiconductor device with a novel structure and favorable characteristics. A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

5.WO/2001/060938ADHESIVE COMPOSITION, PROCESS FOR PRODUCING THE SAME, ADHESIVE FILM MADE WITH THE SAME, SUBSTRATE FOR SEMICONDUCTOR MOUNTING, AND SEMICONDUCTOR DEVICE

WO - 23.08.2001

CIP C08G 59/18 № do pedido PCT/JP2001/001065 Requerente HITACHI CHEMICAL CO., LTD. Inventor INADA, Teiichi

An adhesive composition which comprises (a) an epoxy resin, (b) a hardener, and (c) a polymer incompatible with the epoxy resin and optionally contains (d) a filler and/or (e) a curing accelerator; a process for producing an adhesive composition which comprises mixing (a) an epoxy resin with (b) a hardener and (d) a filler and then mixing the resultant mixture with (c) a polymer incompatible with the epoxy resin; an adhesive film obtained by forming the adhesive composition into a film; a substrate for semiconductor mounting which comprises a wiring board and the adhesive film disposed thereon on its side where chips are to be mounted; and a semiconductor device produced with the adhesive film or the substrate.

6.WO/2011/126334PORTABLE DISPLAY APPARATUS

WO - 13.10.2011

CIP G06F 1/16 № do pedido PCT/KR2011/002470 Requerente KIM, Si-Han Inventor KIM, Si-Han

The present invention relates to a portable display apparatus comprising: at least two housing panels which are provided with upper and lower parts respectively stacked together; and display units mounted on the upper and lower housing panels, respectively, in which the upper and lower housing panels are slidable in the left and right directions and movable in the upward and downward directions relative to one another, such that the display units mounted on the upper and lower housing panels are placed adjacent to one another, wherein the gap between the display units is 0.1 mm to 5 mm when the display units are placed adjacent to one another, and a separate moving means is provided between the upper and lower housing panels. Thus, in order to set the two display units which have been stacked at the same height, it is possible to effectively provide a moving means for movement in the upward and downward directions, together with a sliding means for sliding in the left and right directions. In addition, the separate moving means functions to firmly support the upper housing panel when the housing panels are completely unfolded.

7.WO/2017/222611INTERACTIVE GAMING AMONG A PLURALITY OF PLAYERS SYSTEMS AND METHODS

WO - 28.12.2017

CIP G07F 17/32 № do pedido PCT/US2017/020950 Requerente AG 18, LLC Inventor FRENKEL, Brian

A system for interactive gaming among a plurality of players includes a host computer system and a plurality of player terminals communicably coupled to the host computer system or gaming platform via a network. The plurality of player terminals may be located at a plurality of licensed gaming locations. The plurality of player terminals may be configured to engage the plurality of players in a common interactive game operated by the host computer system. The plurality of player terminals can include means for dispensing player winnings from the player terminal.

8.WO/2010/061723DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME

WO - 03.06.2010

CIP G09G 3/36 № do pedido PCT/JP2009/069142 Requerente SEMICONDUCTOR ENERGY LABORATORY CO., LTD. Inventor UMEZAKI, Atsushi

A gate driver circuit for a display device comprises a shift register. The shift register includes a plurality of flip-flops (200 1 to 200_N). Each of the flip-flops (200_l to 200_N) includes a first transistor (101), a second transistor (102), a third transistor (103), a fourth transistor (104), a fifth transistor (131), a sixth transistor (132), a seventh transistor (133), an eighth transistor (134) a ninth transistor (135), and a capacitor (106). The present invention can decrease the number of transistors that are connected to the capacitor (106).

9.WO/2013/095396CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS

WO - 27.06.2013

CIP H01L 21/316 № do pedido PCT/US2011/066252 Requerente INTEL CORPORATION Inventor KING, Sean

Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

10.WO/2011/055620SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

WO - 12.05.2011

CIP H01L 29/786 № do pedido PCT/JP2010/068105 Requerente SEMICONDUCTOR ENERGY LABORATORY CO., LTD. Inventor YAMAZAKI, Shunpei

An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.

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